Archives for May 2019

What do JasperGold, Stratus, and the Rocketick part of Xcelium have in common? Well, they are all Cadence products, of course. But they also all use Verific as parsers for SystemVerilog, Verilog, and VHDL.

Verific got started twenty years ago, Rob Dekker told me.

Read more at Cadence Breakfast Bytes Blog.