Verific Design Automation, recognized as the leading supplier of hardware description language (HDL) parsers used throughout the semiconductor industry, today announced electronic design automation (EDA) newcomer Vtool has chosen Verific’s parsers for use with its functional verification platform.
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Invionics Unveils VRDM for Rapid Deployment of Verific’s Parsers
Invionics, a company providing software to accelerate integrated circuit (IC) development and design automation, today took the wraps off the VRDM Development Platform that layers a rapid development interface on top of Verific’s industry-standard, IEEE-compliant SystemVerilog and VHDL parsers.
So-ADE Unveils Debugger for Use With Verific Design Automation’s SystemVerilog, VHDL, UPF Parser Platforms
“We’re delighted that So-ADE founders created a product around our parser platform, and they have our full support,” notes Michiel Ligthart, Verific’s president and chief operating officer.
Today’s announcement reinforces Verific’s reach into a wide variety of verification segments, including analysis, emulation, simulation and synthesis.
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Rocketick Renews Parser Platform License
Verific Design Automation, provider of SystemVerilog, VHDL and UPF parsers, today announced Rocketick Technologies Ltd., a leading provider of Verilog simulation acceleration solutions for chip verification, has renewed its license for Verific’s SystemVerilog Parser Platform.
“Verific has been an outstanding partner,” adds Uri Tal, Rocketick’s chief executive officer. “Its software is high quality, as is the support and service. I can’t think of a more responsive and supportive EDA vendor.”
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Verific Design Automation Closes Fifth Consecutive Year of Growth
Verific Design Automation, provider of SystemVerilog, VHDL and UPF parsers, finished its fifth consecutive year of growth with a double-digit increase in revenue.
Read more at finance.yahoo.com
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