Verific today announced full integration of INVIO with its flagship parser platforms. This follows an earlier announcement that it acquired from Invionics Software the INVIO platform, with its high-level level application programming interfaces (APIs) that enable Verific users to simplify and streamline their design environment, accelerating tool development.

Read more at EDACafe.com.

Verific Design Automation today announced Efinix™, an innovator in programmable product platforms and technology, selected its Verilog Parser Platform and register transfer level (RTL) elaborator to serve as the front end to the Efinity™ Integrated Design Environment (IDE).

Read more at MarketWired.

SystemVerilog and VHDL parsers from Verific serve as the front end to Austemper’s software that analyzes, augments and verifies functional safety in system-on-chip (SoC), application specific integrated circuit (ASIC) and intellectual property (IP) designs ensuring they meet functional safety requirements.

Read more at MarketWired.

New Functionality Broadens UPF Parser/Analyzer Capabilities

Verific Design Automation, the recognized leader of SystemVerilog, VHDL and Unified Power Format (UPF) Parser Platforms in production and development use throughout the semiconductor industry, today announced availability of its UPF Elaborator.

Read more at MarketWired.

A startup can shave 12 months or more off the development cycle by outsourcing non-essential elements of product design.

I’m hearing from different sources that investments in electronic design automation (EDA) and semiconductor startups are picking up around the globe and not just in Silicon Valley. That’s welcome news –– and long overdue –– as we move through 2017. With funding come new and innovative products and the cycle of growth to acquisition or other successful outcomes endures.

Read more at EE Times.