news Archives - Verific Design Automation

13 January 2020

Celebrating 20 Years of Exceptional Support

Six Short Interviews with Some of Verific’s Long-Time Customers Highlight Positive Experience

Nanette Collins, public relations consultant for Verific, interviewed several of Verific’s long-time customers and wrote a six-part blog series on their experience with Verific.

27 September 2017

Baum Licenses Verific’s Parser Platform

Baum, a leader in power analysis solutions, today became the newest licensee of Verific Design Automation, the recognized leader of SystemVerilog, VHDL and UPF Parser Platforms in production and development use throughout the semiconductor industry.

Verific Acquires INVIO Platform

Under terms of the agreement, Verific will acquire Invionics Software’s entire INVIO technology portfolio, for electronic design automation (EDA) tools and flows. An R&D group with real-world design experience and a deep understanding of EDA software development will join Verific’s engineering department.

Cutting-edge EDA Startups rely on Verific

Verific to Showcase Three Design Automation Startups With Safety-Features Insertion, Low-Power, Hardware Security Analysis Offerings in Its DAC Booth
Read more at finance.yahoo.com

14 January 2016

UPF 3.0 is Now Official

The new UPF 3.0 standard offers additional enhancements to address and describe power intent of complex systems on chip (SoCs).
Read more at eetimes.com