View source for Design with System Verilog and Verilog 2001 files

'''Q: For a design consisting of a mixture of Verilog 2001 and SystemVerilog input files, should I parse all the files as SystemVerilog?'''

The set of SystemVerilog constructs is a superset of the set of Verilog 2001 constructs. As a corollary, the set of SystemVerilog keywords is a superset of the set of Verilog 2001 keywords.

Parsing a Verilog 2001 file as SystemVerilog will work, as long as the file does not use any SystemVerilog keyword as identifier. If you parse the file as SystemVerilog and run into a syntax error, try parsing it as Verilog 2001.

Another significant difference between Verilog 2001 and SystemVerilog is "compilation units." The default mode of Verilog 2001 is "multi-file" while the default mode of SystemVerilog is "single-file." For more details, please read: [https://www.verific.com/faq/index.php?title=Defined_macros_become_undefined_-_MFCU_vs_SFCU Single/Multi-File Compilation Units].