View source for How to get driving net of an instance

C++:
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#include "Strings.h"
#include "Array.h"
#include "Message.h"
#include "veri_nl_file.h"
#include "DataBase.h"
#include "VeriWrite.h"

#ifdef VERIFIC_NAMESPACE
using namespace Verific ;
#endif

int main()
{
    if (!veri_nl_file::Read("mid.v","work")) return 1 ;
    Netlist *mid = Netlist::PresentDesign() ;
    if (!mid) {
        Message::PrintLine("cannot find any handle to 'mid' netlist") ;
        return 2 ;
    }

    if (!veri_nl_file::Read("top.v","work")) return 3 ;
    Netlist *top = Netlist::PresentDesign() ;
    if (!top) {
        Message::PrintLine("cannot find any handle to 'top' netlist") ;
        return 4 ;
    }

    VeriWrite veriWriter;
    // Write out the design before any modifications
    if (!veriWriter.WriteFile("before.v", top)) return 4 ;

    // Lets get a handle to instance 'mid_bot'
    Instance *bot_inst = mid->GetInst("mid_bot");
    if (!bot_inst) {
        Message::PrintLine("cannot find instance 'mid_bot' netlist") ;
        return 5 ;
    }

    Netlist *bot_nl = bot_inst->View();
    if (!bot_nl) {
        Message::PrintLine("cannot find netlist (view) of instance 'mid_bot'") ;
        return 5 ;
    }

    Port *bot_port = bot_nl->GetPort ("i");
    if (!bot_port) {
        Message::PrintLine("cannot find port") ;
        return 5 ;
    }

    // Get the portref for port 'i' of 'mid_bot'
    PortRef *bot_pr = bot_inst->GetPortRef(bot_port);
    if (!bot_pr) {
        Message::PrintLine("cannot find portref");
        return 5 ;
    }

    Net *net = bot_pr->GetNet();
    if (!net) {
        Message::PrintLine("cannot find net") ;
        return 5 ;
    }

    Netlist *view = bot_inst->Owner();
    if (!view) {
        Message::PrintLine("cannot find view");
        return 5 ;
    }
    if (view->NumOfRefs() > 1) {
        // This netlist is instantiated more than once; need to uniquify it to ensure unique driving nets
        SetIter i ;
        Instance *inst ;
        FOREACH_REFERENCE_OF_NETLIST (view, i, inst) {
            if (!Strings::compare (inst->Name(), "top_mid_2")) continue; // Only interested in instance "top_mid_2"
            Cell *owner = view->Owner() ;
            Netlist *new_netlist = view->Copy() ;
            new_netlist->SetName(0) ; // Force a made-up name for the new netlist
            if (owner) (void) owner->Add(new_netlist) ;
            // Swap the instance to the new netlist
            inst->ReplaceView(new_netlist, 0 /* By port order is faster */, 0 /* By port bit is faster */) ;
            view = new_netlist ;
        }
    }

    Message::PrintLine("**** In Netlist '", view->Name(), "' of cell '", view->Owner()->Name(), "'");
    Message::PrintLine("     Found net '", net->Name(), "'");
    Message::PrintLine("         driving port '", bot_port->Name(), "' of instance '", bot_inst->Name(), "'");

    // Write out the design after uniquification
    if (!veriWriter.WriteFile("after.v", top)) return 4 ;

    return 0 ;
}
 </nowiki>

top.v
 <nowiki>
module top (output topo2, topo1, input topi2, topi1);
  mid top_mid_1 (topo1, topi1);
  mid top_mid_2 (topo2, topi2);
endmodule
 </nowiki>

mid.v
 <nowiki>
module bot (output o, input i);
endmodule

module mid(output mido, input midi);
  bot mid_bot (mido, midi);
endmodule
 </nowiki>

Run Output :
 <nowiki>
-- Reading structural Verilog file 'mid.v' (VNLR-1084)
mid.v(1): INFO: compiling module 'bot' (VNLR-1012)
mid.v(4): INFO: compiling module 'mid' (VNLR-1012)
mid.v(4): INFO: setting 'mid' as the top level module (VNLR-1015)
-- Reading structural Verilog file 'top.v' (VNLR-1084)
top.v(1): INFO: compiling module 'top' (VNLR-1012)
top.v(1): INFO: setting 'top' as the top level module (VNLR-1015)
-- Writing netlist 'top' to Verilog file 'before.v' (VDB-1030)
-- **** In Netlist 'v1' of cell 'mid'
--      Found net 'midi'
--          driving port 'i' of instance 'mid_bot'
-- Writing netlist 'top' to Verilog file 'after.v' (VDB-1030)
 </nowiki>