View source for How to ignore a (not used) parameter/generic in elaboration.

'''Q: How do I specify the elaborator to ignore parameter/generic that is not used?'''

In RTL or static elaboration, parameterized instances are uniquified. For example, this RTL code:
 <nowiki>
module top (a0, a1, b0, b1, c0, c1);
    parameter DUMMY0 = 8;
    parameter DUMMY1 = 16;
    parameter WIDTH = 4;
    input [WIDTH-1 : 0] a0, b0, a1, b1;
    output [WIDTH-1 : 0] c0, c1;

    bot #(.WIDTH(WIDTH), .DUMMY(DUMMY0)) i0 (a0, b0, c0);
    bot #(.WIDTH(WIDTH), .DUMMY(DUMMY1)) i1 (a1, b1, c1);
endmodule

module bot #(parameter WIDTH = 8, parameter DUMMY = 0) (a, b, c);
    input [WIDTH-1 : 0] a, b;
    output [WIDTH-1 : 0] c;
endmodule
 </nowiki>
will be synthesized to:
 <nowiki>
module top (a0, a1, b0, b1, c0, c1);
    input [3:0]a0;
    input [3:0]a1;
    input [3:0]b0;
    input [3:0]b1;
    output [3:0]c0;
    output [3:0]c1;     
    \bot(WIDTH=4,DUMMY=8)  i0 (.a({a0}), .b({b0}), .c({c0}));
    \bot(WIDTH=4,DUMMY=16)  i1 (.a({a1}), .b({b1}), .c({c1}));    
endmodule

module \bot(WIDTH=4,DUMMY=8)  (a, b, c);
    input [3:0]a;
    input [3:0]b;
    output [3:0]c;
endmodule

module \bot(WIDTH=4,DUMMY=16)  (a, b, c);
    input [3:0]a;
    input [3:0]b;
    output [3:0]c;
endmodule
 </nowiki>
In the output netlist, module "\bot(WIDTH=4,DUMMY=8)" and module "\bot(WIDTH=4,DUMMY=16)" are identical because parameter "DUMMY", although having a different value for each instance of module "bot," is not used to determine the logic implementation.

Thus "DUMMY" can be ignored in elaboration.

Use the API "veri_file::SetIgnoreParameter(), in this case:
 <nowiki>
veri_file::SetIgnoreParameter("work", "bot", "DUMMY");
 </nowiki>
The output netlist is now:
 <nowiki>
module top (a0, a1, b0, b1, c0, c1);
    input [3:0]a0;
    input [3:0]a1;
    input [3:0]b0;
    input [3:0]b1;
    output [3:0]c0;
    output [3:0]c1;
    \bot(WIDTH=4)  i0 (.a({a0}), .b({b0}), .c({c0}));
    \bot(WIDTH=4)  i1 (.a({a1}), .b({b1}), .c({c1}));
endmodule

module \bot(WIDTH=4)  (a, b, c);
    input [3:0]a;
    input [3:0]b;
    output [3:0]c;
endmodule
 </nowiki>
For VHDL, the API is "VHDL_file::SetIgnoreGeneric()".