View source for Included files associated with a Verilog source file

'''Q: How do I get the list of included files associated with a Verilog source file?'''

The main utility you require is:
    static Map *veri_file::GetIncludedFiles() ;
It returns a (static) Map *. The map is hashed with char *name of the `include file and the value is the linefile_type from where it was included. Code sample:
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const char *source_file = .... ; // The RTL source file name
// Find the file-id for linefile object of this file:
unsigned file_id = LineFile::GetFileId(source_file);
// Get the name of all the include files:
const Map *all_include_files = veri_file::GetIncludedFiles();
MapIter mi ;
const char *include_file ;
linefile_type source_linefile ;
// Now traverse the Map to find the include files for this file-id:
FOREACH_MAP_ITEM(all_include_files, mi, &include_file, &source_linefile) {
    if (LineFile::GetFileId(source_linefile) == file_id) {
        // Here we found a `include file "include_file" from "source_file"
        // Do what you want to do here... 
    }
}
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Below is a simple example:

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$ cat test.v
module test (
`include "foo_ports.v"
);
endmodule

$ cat test.cpp
#include "veri_file.h"
#include "LineFile.h"
#include "Strings.h"
#include "TextBasedDesignMod.h"
#include "Map.h"

using namespace std ;

#ifdef VERIFIC_NAMESPACE
using namespace Verific ;
#endif

int main()
{
    const char *source_file = "test.v";
    const char *mod_source_file = "mod_test.v";
    const char *included_file = "foo_ports.v";
    if (!veri_file::Analyze(source_file)) return 1 ;

    TextBasedDesignMod tbdm(0) ; // Can modify all files

    // Find the file-id for linefile object of this file:
    unsigned file_id = LineFile::GetFileId(source_file);
    // Get the name of all the include files:
    const Map *all_include_files = veri_file::GetIncludedFiles();
    MapIter mi ;
    const char *include_file ;
    linefile_type source_linefile ;
    // Now traverse the Map to find the include files for this file-id:
    FOREACH_MAP_ITEM(all_include_files, mi, &include_file, &source_linefile) {
        if (LineFile::GetFileId(source_linefile) == file_id) {
            if (Strings::compare(include_file, included_file)) {
                tbdm.InsertAfter(source_linefile, "\n, input [3:0] port1") ;
            }
        }
    }
    tbdm.WriteFile(source_file, mod_source_file) ;

    return 0 ;
}

$ test-linux
-- Analyzing Verilog file 'test.v' (VERI-1482)
test.v(2): INFO: analyzing included file 'foo_ports.v' (VERI-1328)
test.v(2): INFO: back to file 'test.v' (VERI-2320)

$ cat mod_test.v
module test (
`include "foo_ports.v"
, input [3:0] port1
);
endmodule

$
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