View source for Top level module with interface ports

'''Q: How to elaborate top-level module with interface ports.'''

When I elaborate a top-level module with interface ports, Verific issues a warning message and stops the elaboration:

 test.sv(10): WARNING: module 'top' having interface port(s) (I) cannot be elaborated by itself (VERI-1554)

How do I elaborate such modules?


Verilog LRM does not allow (elaboration of) top level modules with interface ports. Interface ports need actual interface instance connected to them to elaborate the design.

However, Verific has a runtime flag "veri_elaborate_top_level_modules_having_interface_ports" which when set will elaborate such designs assuming the default interface.

* C++:
 RuntimeFlags::SetVar("veri_elaborate_top_level_modules_having_interface_ports", 1) ;
* tcl:
 set_runtime_flag "veri_elaborate_top_level_modules_having_interface_ports" 1

  [hoa@awing6 181228]$ cat test.sv
  interface myinterface() ;
    logic foo, bar;
  endinterface
  
  module top(myinterface I[1:0][1:0], input ii[0:1], output oo[1:0]);
  assign I[1][1].foo = ii[0] ;
  assign I[0][0].foo = ii[1] ;
  assign oo[1] = I[1][1].foo ;
  assign oo[0] = I[0][0].foo ;
  endmodule
  [hoa@awing6 181228]$ verific-linux 
  -- (c) Copyright 1999 - 2018 Verific Design Automation Inc. All rights reserved
  % analyze -sysv test.sv
  -- Analyzing Verilog file 'test.sv' (VERI-1482)
  % elaborate
  '''test.sv(10): WARNING: module 'top' having interface port(s) (I) cannot be elaborated by itself (VERI-1554)'''
  % cleanup -all -static
  INFO: All parse-trees and netlists were deleted (CMD-2055)
  % analyze -sysv test.sv
  -- Analyzing Verilog file 'test.sv' (VERI-1482)
  % '''set_runtime_flag "veri_elaborate_top_level_modules_having_interface_ports" 1'''
  INFO: value of runtime flag 'veri_elaborate_top_level_modules_having_interface_ports' is 1 (CMD-2076)
  % elaborate
  test.sv(5): INFO: compiling module 'top' (VERI-1018)
  % exit
  [hoa@awing6 181228]$