View source for Type Range example

C++:
 <nowiki>
/*
 *
 * (c) Copyright 1999 - 2019 Verific Design Automation Inc.
 * All rights reserved.
 *
 * This source code belongs to Verific Design Automation Inc.
 * It is considered trade secret and confidential, and is not to be used
 * by parties who have not received written authorization
 * from Verific Design Automation Inc.
 *
 * Only authorized users are allowed to use, copy and modify
 * this software provided that the above copyright notice
 * remains in all copies of this software.
 *
 *
*/

#include "Map.h"         // Make associated hash table class Map available
#include "Set.h"         // Make associated hash table class Set available

#include "Message.h"     // Make message handlers available

#include "veri_file.h"   // Make verilog reader available

#include "DataBase.h"    // Make (hierarchical netlist) database API available

#ifdef VERIFIC_NAMESPACE
using namespace Verific ;
#endif

int main(int argc, char **argv)
{
    RuntimeFlags::SetVar("db_add_id_vs_netbus_map", 1) ;

    // Now read in top-level design. In case of failure return.
    if (!veri_file::Read("test.sv", "work", veri_file::SYSTEM_VERILOG)) {
        // Here, design analysis and elaboration failed
        return 1 ;
    }

    // Get a handle to the top-level netlist
    Netlist *top = Netlist::PresentDesign() ;
    if (!top) {
        Message::PrintLine("cannot find any handle to the top-level netlist") ;
        return 4 ;
    }

    // Print out module that we have handle to
    Message::Msg(VERIFIC_INFO, 0, top->Linefile(), "top level design is %s(%s)",
                 top->Owner()->Name(), top->Name()) ;

    // Get the id_vs_netbus table
    const Set *out_nets = top->GetIdNets("out") ;
    if (!out_nets) {
        Message::PrintLine("No nets associated with identifier out") ;
        return 5 ;
    }

    SetIter si ;
    DesignObj *net_obj ;
    FOREACH_SET_ITEM(out_nets, si, &net_obj) {
        if (!net_obj) continue ;
        net_obj->Info("Net object name: %s, %s", net_obj->Name(), net_obj->IsNet() ? "net" : "netbus") ;
    }

    // All done.  Wasn't that easy ?
    return 0 ;
}
 </nowiki>

Input Verilog:
 <nowiki>
module struct_test(in, clk, out);
typedef struct {
    logic a;
    logic b;
    logic [5:4] c [4:0];
} my_struct;

input my_struct in [2:0];
output my_struct out [2:0];
input clk;

my_struct r [2:0];
always@(posedge clk)
    r <= in;
assign out = r;
endmodule

 </nowiki>

Run:
 <nowiki>
-- Analyzing Verilog file 'test.sv' (VERI-1482)
test.sv(1): INFO: compiling module 'struct_test' (VERI-1018)
test.sv(1): INFO: top level design is struct_test()
test.sv(9): INFO: Net object name: out[2].a, net
test.sv(9): INFO: Net object name: out[2].b, net
test.sv(9): INFO: Net object name: out[2].c[4], netbus
test.sv(9): INFO: Net object name: out[2].c[3], netbus
test.sv(9): INFO: Net object name: out[2].c[2], netbus
test.sv(9): INFO: Net object name: out[2].c[1], netbus
test.sv(9): INFO: Net object name: out[2].c[0], netbus
test.sv(9): INFO: Net object name: out[1].a, net
test.sv(9): INFO: Net object name: out[1].b, net
test.sv(9): INFO: Net object name: out[1].c[4], netbus
test.sv(9): INFO: Net object name: out[1].c[3], netbus
test.sv(9): INFO: Net object name: out[1].c[2], netbus
test.sv(9): INFO: Net object name: out[1].c[1], netbus
test.sv(9): INFO: Net object name: out[1].c[0], netbus
test.sv(9): INFO: Net object name: out[0].a, net
test.sv(9): INFO: Net object name: out[0].b, net
test.sv(9): INFO: Net object name: out[0].c[4], netbus
test.sv(9): INFO: Net object name: out[0].c[3], netbus
test.sv(9): INFO: Net object name: out[0].c[2], netbus
test.sv(9): INFO: Net object name: out[0].c[1], netbus
test.sv(9): INFO: Net object name: out[0].c[0], netbus
 </nowiki>