Information for "Verilog Port Expressions"
Basic information
| Display title | Verilog Port Expressions |
| Default sort key | Verilog Port Expressions |
| Page length (in bytes) | 6,539 |
| Page ID | 129 |
| Page content language | English (en) |
| Page content model | wikitext |
| Indexing by robots | Allowed |
| Number of redirects to this page | 1 |
Page protection
| Edit | Allow all users (infinite) |
| Move | Allow all users (infinite) |
Edit history
| Page creator | Hoa (Talk | contribs) |
| Date of page creation | 14:58, 22 July 2016 |
| Latest editor | Hoa (Talk | contribs) |
| Date of latest edit | 13:40, 13 February 2023 |
| Total number of edits | 6 |
| Total number of distinct authors | 1 |
| Recent number of edits (within past 90 days) | 0 |
| Recent number of distinct authors | 0 |
