Difference between revisions of "Main Page"
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* [[Design with VHDL-1993 and VHDL-2008 files | VHDL-1993 and VHDL-2008 each has its own IEEE library set. How do I analyze/elaborate a design with a mixture of files of different VHDL dialects (1993 and 2008)?]] | * [[Design with VHDL-1993 and VHDL-2008 files | VHDL-1993 and VHDL-2008 each has its own IEEE library set. How do I analyze/elaborate a design with a mixture of files of different VHDL dialects (1993 and 2008)?]] | ||
* [[How to get module ports from Verilog parsetree | From the Verilog parsetree, how can I get the ports of a module?]] | * [[How to get module ports from Verilog parsetree | From the Verilog parsetree, how can I get the ports of a module?]] | ||
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'''Output''' | '''Output''' | ||
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'''TCL, Perl, Python, Java''' | '''TCL, Perl, Python, Java''' | ||
| + | * [[What languages can I use with Verific software? | What programming languages can I use with Verific software?]] | ||
Revision as of 15:57, 22 July 2016
General
- How do I know what language a Netlist in the netlist database comes from?
- What are the data structures in Verific?
- Does Verific build control and data flow graph (CDFG)?
- Does Verific support cross module references (XMR)?
VHDL, Verilog, Liberty, EDIF
- I'm using -v, -y, .... After Verific is done with the analysis, how do I get a list of all the files being analyzed?
- While looking at a Netlist, is there a clean way to look back at what VeriModule* or VhdlPrimaryUnit* this netlist was derived from?
- Why are the ports in original Verilog file renamed to p1, p2, ....?
- For a design consisting of a mixture of Verilog 2001 and SystemVerilog input files, should I parse all the files as SystemVerilog?
- VHDL-1993 and VHDL-2008 each has its own IEEE library set. How do I analyze/elaborate a design with a mixture of files of different VHDL dialects (1993 and 2008)?
- From the Verilog parsetree, how can I get the ports of a module?
Output
TCL, Perl, Python, Java
