Difference between revisions of "Main Page"
From Verific Design Automation FAQ
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'''VHDL, Verilog, Liberty, EDIF''' | '''VHDL, Verilog, Liberty, EDIF''' | ||
* [[How to get all Verilog files being analyzed | I'm using -v, -y, .... After Verific is done with the analysis, how do I get a list of all the files being analyzed?]] | * [[How to get all Verilog files being analyzed | I'm using -v, -y, .... After Verific is done with the analysis, how do I get a list of all the files being analyzed?]] | ||
| + | * [[Included files associated with a Verilog source file | How do I get the list of included files associated with a Verilog source file?]] | ||
* [[What VeriModule* or VhdlPrimaryUnit* the Netlist comes from? | While looking at a Netlist, is there a clean way to look back at what VeriModule* or VhdlPrimaryUnit* this netlist was derived from?]] | * [[What VeriModule* or VhdlPrimaryUnit* the Netlist comes from? | While looking at a Netlist, is there a clean way to look back at what VeriModule* or VhdlPrimaryUnit* this netlist was derived from?]] | ||
* [[Verilog ports being renamed | Why are the ports in original Verilog file renamed to p1, p2, ....?]] | * [[Verilog ports being renamed | Why are the ports in original Verilog file renamed to p1, p2, ....?]] | ||
Revision as of 14:31, 26 July 2016
General
- How do I know what language a Netlist in the netlist database comes from?
- What are the data structures in Verific?
- How do I remove all Verific data structures in memory?
- Does Verific build control and data flow graph (CDFG)?
- Does Verific support cross module references (XMR)?
VHDL, Verilog, Liberty, EDIF
- I'm using -v, -y, .... After Verific is done with the analysis, how do I get a list of all the files being analyzed?
- How do I get the list of included files associated with a Verilog source file?
- While looking at a Netlist, is there a clean way to look back at what VeriModule* or VhdlPrimaryUnit* this netlist was derived from?
- Why are the ports in original Verilog file renamed to p1, p2, ....?
- For a design consisting of a mixture of Verilog 2001 and SystemVerilog input files, should I parse all the files as SystemVerilog?
- VHDL-1993 and VHDL-2008 each has its own IEEE library set. How do I analyze/elaborate a design with a mixture of files of different VHDL dialects (1993 and 2008)?
- From the Verilog parsetree, how can I get the ports of a module?
Output
TCL, Perl, Python, Java
