Difference between revisions of "Verific data structures"
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The parsetree is just another representation of the design. It contains the exact information as in the RTL files, only in a machine-readable format. Because each language (Verilog or VHDL) has its own constructs, each language has its own parsetree. | The parsetree is just another representation of the design. It contains the exact information as in the RTL files, only in a machine-readable format. Because each language (Verilog or VHDL) has its own constructs, each language has its own parsetree. | ||
| − | :The parsetree is the result of veri_file::Analyze()/vhdl_file:: | + | :The parsetree is the result of veri_file::Analyze()/vhdl_file::Analyze(). |
:The design parsetree can be "statically elaborated." These are some of the operations during static elaboration process: | :The design parsetree can be "statically elaborated." These are some of the operations during static elaboration process: | ||
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| − | Note that during RTL elaboration, Verific software creates a netlist directly from the parse tree. It does not build a control and data flow graph (CDFG). If an application needs a CDFG, it will have to define the graph structure and use Verific parse tree traversal routines to build the graph. | + | Note that during RTL elaboration, Verific software creates a netlist directly from the parse tree. It does not build a control and data flow graph (CDFG). If an application needs a CDFG, it will have to define the graph structure and use Verific parse tree traversal routines or Verific Netlist database traversal routines to build the graph. |
Latest revision as of 15:13, 27 April 2020
Q: What are the data structures in Verific?
There are 2 data structures in Verific: parsetree and netlist database.
- Parsetree
The parsetree is just another representation of the design. It contains the exact information as in the RTL files, only in a machine-readable format. Because each language (Verilog or VHDL) has its own constructs, each language has its own parsetree.
- The parsetree is the result of veri_file::Analyze()/vhdl_file::Analyze().
- The design parsetree can be "statically elaborated." These are some of the operations during static elaboration process:
- Unrolling "generate" loops.
- Evaluating constant expressions.
- Uniquifying instances of parameterized modules/entities.
- The result of static elaboration is a modified parsetree.
- The parsetree supports all constructs of the language.
- Netlist Database
The synthesizable subset of the parsetree can go through "RTL elaboration" (or "synthesis"). The result is the "netlist database," consisting of "hardware" components: libraries, cells, netlists, nets, ports, instances, operators (adders, muxes, ...), and primitives (ands, ors, xors, ...). The netlist database is language-independent. The contents of the netlist database can be written out in various structural languages: Verilog, VHDL, EDIF, BLIF. In general, the output netlist from the netlist database does not look anything like the RTL input files.
The netlist database is the result of veri_file::Elaborate()/vhdl_file::Elaborate() API (after veri_file::Analyze()/vhdl_file::Analyze()).
RTL elaboration supports the synthesizable subset of the language.
Note that during RTL elaboration, Verific software creates a netlist directly from the parse tree. It does not build a control and data flow graph (CDFG). If an application needs a CDFG, it will have to define the graph structure and use Verific parse tree traversal routines or Verific Netlist database traversal routines to build the graph.
