Difference between revisions of "Message handling"
From Verific Design Automation FAQ
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You can set any message to any type below: | You can set any message to any type below: | ||
| + | <nowiki> | ||
| + | VERIFIC_NONE, // print no prefix | ||
| + | VERIFIC_ERROR, // print ERROR: | ||
| + | VERIFIC_WARNING, // print WARNING: | ||
| + | VERIFIC_IGNORE, // ignore message (do not print message): | ||
| + | VERIFIC_INFO, // print INFO: | ||
| + | VERIFIC_COMMENT, // print -- | ||
| + | VERIFIC_PROGRAM_ERROR // print PROGRAM_ERROR | ||
| + | </nowiki> | ||
| + | For C++, use the following APIs: | ||
| + | <nowiki> | ||
| + | Message::SetMessageType() - Force a message type by message id | ||
| + | Message::GetMessageType() - Get the message type by message id | ||
| + | Message::ClearMessageType() - Clear a message type by message id | ||
| + | Message::SetAllMessageType() - Force all messages of type 'orig' to behave as type 'type'. | ||
| + | Message::ClearAllMessageTypes() - Clear all forced message types | ||
| + | </nowiki> | ||
| + | For Tcl, use the following commands: | ||
| + | <nowiki> | ||
| + | setmsgtype | ||
| + | clearmsgtype | ||
| + | </nowiki> | ||
| + | Some Perl command examples: | ||
| + | <nowiki> | ||
| + | # ignore message VNLR-1015 | ||
| + | Verific::Message::SetMessageType("VNLR-1015", $Verific::VERIFIC_IGNORE); | ||
| + | # ignore all warning messages | ||
| + | Verific::Message::SetAllMessageType($Verific::VERIFIC_WARNING, $Verific::VERIFIC_IGNORE); | ||
| + | </nowiki> | ||
| + | Note that downgrading an error may have unpredictable/undesirable results. | ||
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| − | + | '''Q: How do I get messages with more details?''' | |
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| − | For | + | For "syntax error" messages, you can get messages with more details by enabling compile flag "VERIFIC_PRODUCE_VERBOSE_SYNTAX_ERROR_MESSAGE" or its runtime equivalent "verific_produce_verbose_syntax_error_message." |
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| − | + | ||
| − | + | With these flags enabled, for syntax errors, the parsers will print the whole line and point to the token where the issue is. they also print the expected tokens that may fix the issue. | |
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| − | + | For example, with: | |
| + | <nowiki> | ||
| + | 1. module test (input c, output reg o) ; | ||
| + | 2. always@(*) | ||
| + | 3. unique priority case (c) | ||
| + | 4. 1'b0 : o = 1'b1 ; | ||
| + | 5. 1'b1 : o = 1'b0 ; | ||
| + | 6. endcase | ||
| + | 7. endmodule | ||
| + | </nowiki> | ||
| + | By default, the Verilog parser outputs: | ||
| + | <nowiki> | ||
| + | -- Analyzing Verilog file 'test.v' (VERI-1482) | ||
| + | test.v(3): ERROR: syntax error near 'priority' (VERI-1137) | ||
| + | test.v(3): ERROR: SystemVerilog keyword priority used in incorrect context (VERI-2344) | ||
| + | test.v(4): ERROR: syntax error near '=' (VERI-1137) | ||
| + | test.v(5): ERROR: syntax error near '=' (VERI-1137) | ||
| + | test.v(3): ERROR: 'c' is not a constant (VERI-1188) | ||
| + | test.v(4): ERROR: 'o' is not a type (VERI-1281) | ||
| + | test.v(5): ERROR: 'o' is not a type (VERI-1281) | ||
| + | test.v(7): ERROR: module 'test' ignored due to previous errors (VERI-1072) | ||
| + | ERROR: analyze: failed (CMD-1014) | ||
| + | </nowiki> | ||
| + | |||
| + | With "verific_produce_verbose_syntax_error_message" enabled, you'll see: | ||
| + | <nowiki> | ||
| + | -- Analyzing Verilog file 'test.v' (VERI-1482) | ||
| + | test.v(3): INFO: unique priority case (c) (VERI-2124) | ||
| + | test.v(3): INFO: ^ (VERI-2124) | ||
| + | test.v(3): ERROR: syntax error near 'priority', expecting 'case' or 'casex' or 'casez' or 'if' (VERI-1137) | ||
| + | test.v(3): ERROR: SystemVerilog keyword priority used in incorrect context (VERI-2344) | ||
| + | test.v(4): INFO: 1'b0 : o = 1'b1 ; (VERI-2124) | ||
| + | test.v(4): INFO: ^ (VERI-2124) | ||
| + | test.v(4): ERROR: syntax error near '=' (VERI-1137) | ||
| + | test.v(5): INFO: 1'b1 : o = 1'b0 ; (VERI-2124) | ||
| + | test.v(5): INFO: ^ (VERI-2124) | ||
| + | test.v(5): ERROR: syntax error near '=' (VERI-1137) | ||
| + | test.v(3): ERROR: 'c' is not a constant (VERI-1188) | ||
| + | test.v(4): ERROR: 'o' is not a type (VERI-1281) | ||
| + | test.v(5): ERROR: 'o' is not a type (VERI-1281) | ||
| + | test.v(7): ERROR: module 'test' ignored due to previous errors (VERI-1072) | ||
| + | ERROR: analyze: failed (CMD-1014) | ||
| + | </nowiki> | ||
Revision as of 16:47, 2 June 2020
Q: How do I upgrade/downgrade messages from Verific?
Verific message table, with notation as whether the error can be safely downgraded:
(Access to Verific On-line Documentation requires login. Contact Verific if you don't know/don't have credentials).
You can set any message to any type below:
VERIFIC_NONE, // print no prefix VERIFIC_ERROR, // print ERROR: VERIFIC_WARNING, // print WARNING: VERIFIC_IGNORE, // ignore message (do not print message): VERIFIC_INFO, // print INFO: VERIFIC_COMMENT, // print -- VERIFIC_PROGRAM_ERROR // print PROGRAM_ERROR
For C++, use the following APIs:
Message::SetMessageType() - Force a message type by message id Message::GetMessageType() - Get the message type by message id Message::ClearMessageType() - Clear a message type by message id Message::SetAllMessageType() - Force all messages of type 'orig' to behave as type 'type'. Message::ClearAllMessageTypes() - Clear all forced message types
For Tcl, use the following commands:
setmsgtype clearmsgtype
Some Perl command examples:
# ignore message VNLR-1015
Verific::Message::SetMessageType("VNLR-1015", $Verific::VERIFIC_IGNORE);
# ignore all warning messages
Verific::Message::SetAllMessageType($Verific::VERIFIC_WARNING, $Verific::VERIFIC_IGNORE);
Note that downgrading an error may have unpredictable/undesirable results.
Q: How do I get messages with more details?
For "syntax error" messages, you can get messages with more details by enabling compile flag "VERIFIC_PRODUCE_VERBOSE_SYNTAX_ERROR_MESSAGE" or its runtime equivalent "verific_produce_verbose_syntax_error_message."
With these flags enabled, for syntax errors, the parsers will print the whole line and point to the token where the issue is. they also print the expected tokens that may fix the issue.
For example, with:
1. module test (input c, output reg o) ; 2. always@(*) 3. unique priority case (c) 4. 1'b0 : o = 1'b1 ; 5. 1'b1 : o = 1'b0 ; 6. endcase 7. endmodule
By default, the Verilog parser outputs:
-- Analyzing Verilog file 'test.v' (VERI-1482) test.v(3): ERROR: syntax error near 'priority' (VERI-1137) test.v(3): ERROR: SystemVerilog keyword priority used in incorrect context (VERI-2344) test.v(4): ERROR: syntax error near '=' (VERI-1137) test.v(5): ERROR: syntax error near '=' (VERI-1137) test.v(3): ERROR: 'c' is not a constant (VERI-1188) test.v(4): ERROR: 'o' is not a type (VERI-1281) test.v(5): ERROR: 'o' is not a type (VERI-1281) test.v(7): ERROR: module 'test' ignored due to previous errors (VERI-1072) ERROR: analyze: failed (CMD-1014)
With "verific_produce_verbose_syntax_error_message" enabled, you'll see:
-- Analyzing Verilog file 'test.v' (VERI-1482) test.v(3): INFO: unique priority case (c) (VERI-2124) test.v(3): INFO: ^ (VERI-2124) test.v(3): ERROR: syntax error near 'priority', expecting 'case' or 'casex' or 'casez' or 'if' (VERI-1137) test.v(3): ERROR: SystemVerilog keyword priority used in incorrect context (VERI-2344) test.v(4): INFO: 1'b0 : o = 1'b1 ; (VERI-2124) test.v(4): INFO: ^ (VERI-2124) test.v(4): ERROR: syntax error near '=' (VERI-1137) test.v(5): INFO: 1'b1 : o = 1'b0 ; (VERI-2124) test.v(5): INFO: ^ (VERI-2124) test.v(5): ERROR: syntax error near '=' (VERI-1137) test.v(3): ERROR: 'c' is not a constant (VERI-1188) test.v(4): ERROR: 'o' is not a type (VERI-1281) test.v(5): ERROR: 'o' is not a type (VERI-1281) test.v(7): ERROR: module 'test' ignored due to previous errors (VERI-1072) ERROR: analyze: failed (CMD-1014)
