Difference between revisions of "Notes on analysis"

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(Created page with "This is a place holder for notes regarding analysis of System Verilog designs. Can I use veri_file::Analyze to read SV input files one by one? Yes. But if you have multiple...")
 
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This is a place holder for notes regarding analysis of System Verilog designs.
 
This is a place holder for notes regarding analysis of System Verilog designs.
  
Can I use veri_file::Analyze to read SV input files one by one?
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First, please read
 +
 
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''Can I use veri_file::Analyze to read System Verilog input files one by one?''
 
   
 
   
 
Yes. But if you have multiple files, it’s better to use veri_file::AnalyzeMultipleFiles().
 
Yes. But if you have multiple files, it’s better to use veri_file::AnalyzeMultipleFiles().
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veri_file::AnalyzeMultipleFiles(), besides analyzing each files, also:
 
veri_file::AnalyzeMultipleFiles(), besides analyzing each files, also:
 
   
 
   
- opens and ends the compilation unit
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* opens and ends the compilation unit
- processes –v and –y options
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* processes –v and –y options
- removes include directories
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* removes include directories
- processes root module
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* processes root module
- undefines user-defined macros
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* undefines user-defined macros
- resets compile directives (e.g. `default_nettype, `timescale)
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* resets compile directives (e.g. `default_nettype, `timescale)
 
   
 
   
If you use veri_file::Analyze() to analyze files one by one. After parsing all the files and before elaboration, you’ll need to call:
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If you use veri_file::Analyze() to analyze files one by one, after parsing all the files and before elaboration, you’ll need to call these APIs:
 
   
 
   
- veri_file::ProcessUserLibraries()
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* veri_file::ProcessUserLibraries()
- veri_file::RemoveAllIncludeDirs()
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* veri_file::RemoveAllIncludeDirs()
- veri_file::EndCompilationUnit ()
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* veri_file::EndCompilationUnit ()

Revision as of 09:31, 9 July 2021

This is a place holder for notes regarding analysis of System Verilog designs.

First, please read

Can I use veri_file::Analyze to read System Verilog input files one by one?

Yes. But if you have multiple files, it’s better to use veri_file::AnalyzeMultipleFiles().

veri_file::AnalyzeMultipleFiles(), besides analyzing each files, also:

  • opens and ends the compilation unit
  • processes –v and –y options
  • removes include directories
  • processes root module
  • undefines user-defined macros
  • resets compile directives (e.g. `default_nettype, `timescale)

If you use veri_file::Analyze() to analyze files one by one, after parsing all the files and before elaboration, you’ll need to call these APIs:

  • veri_file::ProcessUserLibraries()
  • veri_file::RemoveAllIncludeDirs()
  • veri_file::EndCompilationUnit ()