Difference between revisions of "Notes on analysis"
(Created page with "This is a place holder for notes regarding analysis of System Verilog designs. Can I use veri_file::Analyze to read SV input files one by one? Yes. But if you have multiple...") |
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| − | + | First, please read this article: [[Defined macros become undefined - MFCU vs SFCU]]. | |
| − | Can I use veri_file::Analyze to read | + | '''Q: Can I use 'veri_file::Analyze()' to read SystemVerilog input files one by one, all of them belonging to one compilation unit?''' |
| − | Yes. But if you have multiple files, it’s better to use veri_file::AnalyzeMultipleFiles(). | + | Yes. But if you have multiple files, it’s better to use 'veri_file::AnalyzeMultipleFiles()'. |
| − | veri_file::AnalyzeMultipleFiles(), besides analyzing each | + | 'veri_file::AnalyzeMultipleFiles()', besides analyzing each file, also: |
| − | + | * opens and ends the compilation unit | |
| − | + | * processes –v and –y options | |
| − | + | * removes include directories | |
| − | + | * processes root module | |
| − | + | * undefines user-defined macros, including command-line macros | |
| − | + | * resets compile directives (e.g. `default_nettype, `timescale) | |
| − | If you use veri_file::Analyze() to analyze | + | If you use 'veri_file::Analyze()' to analyze each file one by one, after all the calls to 'veri_file::Analyze(), depending on the application, you may want to run veri_file::RemoveAllIncludeDirs() and veri_file::EndCompilationUnit(). |
| − | + | ||
| − | + | If the application calls any elaboration API (e.g. veri_file::Elaborate()), there is no need to call veri_file::RemoveAllIncludeDirs() and veri_file::EndCompilationUnit() because the elaboration API will call those APIs before actual elaboration. | |
| − | + | ||
| − | + | The TCL command 'analyze' uses the API 'veri_file::AnalyzeMultipleFiles()'. In other words, it assumes a complete compilation unit for each execution. | |
Latest revision as of 20:53, 31 October 2023
First, please read this article: Defined macros become undefined - MFCU vs SFCU.
Q: Can I use 'veri_file::Analyze()' to read SystemVerilog input files one by one, all of them belonging to one compilation unit?
Yes. But if you have multiple files, it’s better to use 'veri_file::AnalyzeMultipleFiles()'.
'veri_file::AnalyzeMultipleFiles()', besides analyzing each file, also:
- opens and ends the compilation unit
- processes –v and –y options
- removes include directories
- processes root module
- undefines user-defined macros, including command-line macros
- resets compile directives (e.g. `default_nettype, `timescale)
If you use 'veri_file::Analyze()' to analyze each file one by one, after all the calls to 'veri_file::Analyze(), depending on the application, you may want to run veri_file::RemoveAllIncludeDirs() and veri_file::EndCompilationUnit().
If the application calls any elaboration API (e.g. veri_file::Elaborate()), there is no need to call veri_file::RemoveAllIncludeDirs() and veri_file::EndCompilationUnit() because the elaboration API will call those APIs before actual elaboration.
The TCL command 'analyze' uses the API 'veri_file::AnalyzeMultipleFiles()'. In other words, it assumes a complete compilation unit for each execution.
