Difference between revisions of "Simple example of visitor pattern"

Latest revision as of 15:04, 6 September 2024

Example 1:

$ cat test.cpp
#include <iostream>
#include "veri_file.h"
#include "VeriModule.h"
#include "VeriVisitor.h"
#include "VeriConstVal.h"
#include "Map.h"
#include "Strings.h"

#ifdef VERIFIC_NAMESPACE
using namespace Verific ;
#endif

class MyVisitor : public VeriVisitor
{
public:
    MyVisitor() : VeriVisitor() { }
    virtual ~MyVisitor() { }

    virtual void VERI_VISIT(VeriConst, node)
    {
        char *str = node.GetPrettyPrintedString() ;
        node.Info("Got expression: %s", str) ;
        Strings::free(str) ;
    }
} ;

int main (int argc, char **argv)
{
    const char *file_name = "test.sv" ; // defaulf input filename
    if (argc > 1) file_name = argv[1] ; // Set the file name as specified by the user
    // veri_file::Analyze(const char *file_name, unsigned verilog_mode=VERILOG_2K, const char *lib_name="work", unsigned cu_mode=NO_MODE) ;
    if (!veri_file::Analyze(file_name, veri_file::SYSTEM_VERILOG)) return 1 ;

    // if (!veri_file::ElaborateAllStatic()) return 1 ;

    MyVisitor mv ;

    MapIter mi ;
    VeriModule *mod ;
    FOREACH_VERILOG_MODULE(mi, mod) if (mod) mod->Accept(mv) ;

    return 0 ;
}

$ cat test.sv
module test ;
    (* a = 1, b = 2.6 *) wire w ;
    assign w = 2'b00 ;
endmodule

$ test-linux
-- Analyzing Verilog file 'test.sv' (VERI-1482)
test.sv(2): INFO: Got expression: 1
test.sv(2): INFO: Got expression: 2.6
test.sv(3): INFO: Got expression: 2'b0
$
 

Example 2:

$ cat test.cpp
#include <iostream>
#include "veri_file.h"
#include "VeriModule.h"
#include "VeriVisitor.h"
#include "VeriExpression.h"
#include "VeriId.h"
#include "Strings.h"

#ifdef VERIFIC_NAMESPACE
using namespace Verific ;
#endif

class MyVisitor : public VeriVisitor
{
public:
    MyVisitor() : VeriVisitor() { }
    virtual ~MyVisitor() { }

    virtual void VERI_VISIT(VeriBindDirective, node)
    {
        char *str = node.GetPrettyPrintedString() ;
        std::cout << "    bind directive: " << str;
        Strings::free(str) ;
        VeriModuleItem *verimoduleitem = node.GetInstantiation();
        if (verimoduleitem->IsInstantiation()) {
            VeriModuleInstantiation *instantiation = static_cast <VeriModuleInstantiation *>(verimoduleitem);
            str = instantiation->GetPrettyPrintedString() ;
            std::cout << "        instantiation: " << str ;
            VeriModule *mod = instantiation->GetInstantiatedModule();
            if (mod) {
                std::cout << "            instantiated module: " << mod->Name() << "\n";;
            }
            Array *ids = instantiation->GetIds();
            unsigned i;
            VeriInstId *instid;
            FOREACH_ARRAY_ITEM (ids, i, instid) {
                std::cout << "            instance name: " << instid->Name() << "\n";;
            }
            Strings::free(str) ;
        }
        Array *target_inst_list = node.GetTargetInstanceList();
        unsigned i;
        VeriExpression *target_instance ;
        FOREACH_ARRAY_ITEM(target_inst_list, i, target_instance) {
            if (!target_instance) continue ;
            char *str = target_instance->GetPrettyPrintedString() ;
            std::cout << "        target_instance: " << str;
            Strings::free(str) ;
            std::cout << "\n";
        }
    }
} ;

int main(int argc, char **argv)
{
    if (!veri_file::Analyze("test.v", veri_file::SYSTEM_VERILOG)) return 1 ;

    MyVisitor mv ;

    MapIter mi ;
    VeriModule *mod ;
    FOREACH_VERILOG_MODULE(mi, mod) if (mod) mod->Accept(mv) ;

    return 0 ;
}

$ cat test.v
module test;
  sub inst();
endmodule

module foo;
endmodule

bind test.inst foo i_foo(.*);

$ test-linux
-- Analyzing Verilog file 'test.v' (VERI-1482)
    bind directive: bind test.inst foo i_foo (.* ) ;
        instantiation: foo i_foo (.* ) ;
            instantiated module: foo
            instance name: i_foo
        target_instance: test.inst

$