Difference between revisions of "Main Page"
From Verific Design Automation FAQ
| Line 12: | Line 12: | ||
* [[Included files associated with a Verilog source file | Verilog: How do I get the list of included files associated with a Verilog source file?]] | * [[Included files associated with a Verilog source file | Verilog: How do I get the list of included files associated with a Verilog source file?]] | ||
* [[Prettyprint to a string | Verilog: How to prettyprint a parsetree node to a string.]] | * [[Prettyprint to a string | Verilog: How to prettyprint a parsetree node to a string.]] | ||
| + | * [[How to get type/initial value of parameters | Verilog: How to get type/initial value of parameters.]] | ||
* [[Verilog ports being renamed | Verilog: Why are the ports in original Verilog file renamed to p1, p2, ....?]] | * [[Verilog ports being renamed | Verilog: Why are the ports in original Verilog file renamed to p1, p2, ....?]] | ||
* [[Design with System Verilog and Verilog 2001 files | Verilog: For a design consisting of a mixture of Verilog 2001 and SystemVerilog input files, should I parse all the files as SystemVerilog?]] | * [[Design with System Verilog and Verilog 2001 files | Verilog: For a design consisting of a mixture of Verilog 2001 and SystemVerilog input files, should I parse all the files as SystemVerilog?]] | ||
Revision as of 14:49, 26 October 2016
General
- How do I know what language a Netlist in the netlist database comes from?
- What are the data structures in Verific?
- How do I remove all Verific data structures in memory?
- Does Verific build control and data flow graph (CDFG)?
- Does Verific support cross module references (XMR)?
- Are there options to control Verific software's behavior?
- How do I downgrade/upgrade messages from Verific?
VHDL, Verilog (and System Verilog), Liberty, EDIF
- Verilog: I'm using -v, -y, .... After Verific is done with the analysis, how do I get a list of all the files being analyzed?
- Verilog: How do I get the list of included files associated with a Verilog source file?
- Verilog: How to prettyprint a parsetree node to a string.
- Verilog: How to get type/initial value of parameters.
- Verilog: Why are the ports in original Verilog file renamed to p1, p2, ....?
- Verilog: For a design consisting of a mixture of Verilog 2001 and SystemVerilog input files, should I parse all the files as SystemVerilog?
- Verilog: From the Verilog parsetree, how can I get the ports of a module?
- Verilog: Does Verific replace constant expressions with their respective values?
- Verilog: Support for SystemVerilog semaphore/process/mailbox constructs.
- VHDL: VHDL-1993 and VHDL-2008 each has its own IEEE library set. How do I analyze/elaborate a design with a mixture of files of different VHDL dialects (1993 and 2008)?
- Verilog/VHDL: While looking at a Netlist, is there a clean way to look back at what VeriModule* or VhdlPrimaryUnit* this netlist was derived from?
Output
TCL, Perl, Python, Java
