Difference between revisions of "Main Page"

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* [[Instance - Module binding order | Verilog: What is the order of binding modules to instances?]]
 
* [[Instance - Module binding order | Verilog: What is the order of binding modules to instances?]]
 
* [[Constant expression replacement | Verilog: Does Verific replace constant expressions with their respective values?]]
 
* [[Constant expression replacement | Verilog: Does Verific replace constant expressions with their respective values?]]
* [[Defined macros become undefined - MFCU vs SFCU | SystemVerilog: Why does Verific complain about undefined macros for macros defined in a different file?]]
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* [[Defined macros become undefined - MFCU vs SFCU | SystemVerilog: Why does Verific complain about undefined macros for macros defined in a different file (Compilation Unit)?]]
 
* [[How to get enums from Verilog parsetree | SystemVerilog: From the parsetree, how can I get the enums declared in a module?]]
 
* [[How to get enums from Verilog parsetree | SystemVerilog: From the parsetree, how can I get the enums declared in a module?]]
 
* [[How to identify packages being imported into a module | SystemVerilog: How do I identify packages being imported into a module?]]
 
* [[How to identify packages being imported into a module | SystemVerilog: How do I identify packages being imported into a module?]]

Revision as of 10:47, 12 February 2019

General

Input: VHDL, Verilog (and SystemVerilog), Liberty, EDIF

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Output

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