Difference between revisions of "Main Page"
From Verific Design Automation FAQ
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* [[General]] | * [[General]] | ||
* [[VHDL, Verilog, Liberty, EDIF]] | * [[VHDL, Verilog, Liberty, EDIF]] | ||
* [[Output]] | * [[Output]] | ||
* [[TCL, Perl, Python, Java]] | * [[TCL, Perl, Python, Java]] | ||
