Difference between revisions of "Main Page"
From Verific Design Automation FAQ
| Line 1: | Line 1: | ||
| − | General | + | '''General''' |
| − | * [[How do I know what language a Netlist in the netlist database comes from?]] | + | * [[General | How do I know what language a Netlist in the netlist database comes from?]] |
| − | * [[What are the data structures in Verific?]] | + | * [[General | What are the data structures in Verific?]] |
| − | * [[Does Verific support cross module references (XMR)?]] | + | * [[General | Does Verific support cross module references (XMR)?]] |
* [[VHDL, Verilog, Liberty, EDIF]] | * [[VHDL, Verilog, Liberty, EDIF]] | ||
* [[Output]] | * [[Output]] | ||
* [[TCL, Perl, Python, Java]] | * [[TCL, Perl, Python, Java]] | ||
Revision as of 12:58, 7 July 2016
General
