Difference between revisions of "Main Page"
From Verific Design Automation FAQ
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* [[Tcl library path| How to correct building (linking) issue "/usr/bin/ld: cannot find -ltcl"]] | * [[Tcl library path| How to correct building (linking) issue "/usr/bin/ld: cannot find -ltcl"]] | ||
| − | '''VHDL, Verilog (and SystemVerilog), Liberty, EDIF''' | + | '''Input: VHDL, Verilog (and SystemVerilog), Liberty, EDIF''' |
* [[How to get all Verilog files being analyzed | Verilog: I'm using -v, -y, .... After Verific is done with the analysis, how do I get a list of all the files being analyzed?]] | * [[How to get all Verilog files being analyzed | Verilog: I'm using -v, -y, .... After Verific is done with the analysis, how do I get a list of all the files being analyzed?]] | ||
* [[Included files associated with a Verilog source file | Verilog: How do I get the list of included files associated with a Verilog source file?]] | * [[Included files associated with a Verilog source file | Verilog: How do I get the list of included files associated with a Verilog source file?]] | ||
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* [[How to ignore parameters/generics in elaboration | Verilog/VHDL: Is there a way to tell the elaborator to ignore certain parameters/generics so that the unit/module is not uniquified?]] | * [[How to ignore parameters/generics in elaboration | Verilog/VHDL: Is there a way to tell the elaborator to ignore certain parameters/generics so that the unit/module is not uniquified?]] | ||
* [[How to check for errors in analysis/elaboration | Verilog/VHDL: Is there a way to tell if the analysis/elaboration process has errors?]] | * [[How to check for errors in analysis/elaboration | Verilog/VHDL: Is there a way to tell if the analysis/elaboration process has errors?]] | ||
| + | |||
| + | '''Netlist Database''' | ||
'''Output''' | '''Output''' | ||
Revision as of 15:58, 24 August 2018
General
- How do I know what language a Netlist in the netlist database comes from?
- What are the data structures in Verific?
- How do I remove all Verific data structures in memory?
- Does Verific build control and data flow graph (CDFG)?
- Does Verific support cross module references (XMR)?
- Are there options to control Verific software's behavior?
- How do I downgrade/upgrade messages from Verific?
- How do I tell the version of a Verific software release?
- How to correct building (linking) issue "/usr/bin/ld: cannot find -ltcl"
Input: VHDL, Verilog (and SystemVerilog), Liberty, EDIF
- Verilog: I'm using -v, -y, .... After Verific is done with the analysis, how do I get a list of all the files being analyzed?
- Verilog: How do I get the list of included files associated with a Verilog source file?
- Verilog: How to prettyprint a parsetree node to a string.
- Verilog: How to get type/initial value of parameters.
- Verilog: Why are the ports in original Verilog file renamed to p1, p2, ....?
- Verilog: For a design consisting of a mixture of Verilog 2001 and SystemVerilog input files, should I parse all the files as SystemVerilog?
- Verilog: From the Verilog parsetree, how can I get the ports of a module?
- Verilog: From the parsetree, how can I get the enums declared in a module?
- Verilog: How do I change the name of an id (VeriidDef) in Verilog parsetree?
- Verilog: How do I get the library that contains the module nested inside another module?
- Verilog: How do I get linefile information of macro definitions?
- Verilog: How do I get port dimensions?
- Verilog: How do I identify packages being imported into a module?
- Verilog: What is the order of binding modules to instances?
- Verilog: Does Verific replace constant expressions with their respective values?
- Verilog: Support for SystemVerilog semaphore/process/mailbox constructs.
- VHDL: VHDL-1993 and VHDL-2008 each has its own IEEE library set. How do I analyze/elaborate a design with a mixture of files of different VHDL dialects (1993 and 2008)?
- Verilog/VHDL: For a Netlist in the netlist database, is there a clean way to look back at what VeriModule* or VhdlPrimaryUnit* the Netlist was derived from?
- Verilog/VHDL: Is there a way to tell the elaborator to ignore certain parameters/generics so that the unit/module is not uniquified?
- Verilog/VHDL: Is there a way to tell if the analysis/elaboration process has errors?
Netlist Database
Output
TCL, Perl, Python, Java
