Difference between revisions of "What are the data structures in Verific?"
From Verific Design Automation FAQ
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There are 2 data structures in Verific: parsetree and netlist database. | There are 2 data structures in Verific: parsetree and netlist database. | ||
| − | # The parsetree is just another representation of the design. It contains the exact information as in the RTL files, only in a machine-readable format. Because each language (Verilog or VHDL) has its own constructs, each language has its own parsetree. <br /><br />The parsetree is the result of veri_file::Analyze()/vhdl_file::Analyze(). <br /><br />The design parsetree can be "statically elaborated." These are some of the operations during static elaboration process:<br /><br />* Unrolling "generate" loops.<br />* Evaluating constant expressions.<br />* Uniquifying instances of parameterized modules/entities.<br /><br />The result of static elaboration is a modified parsetree.<br /><br />The parsetree supports all constructs of the language. | + | # The parsetree is just another representation of the design. It contains the exact information as in the RTL files, only in a machine-readable format. Because each language (Verilog or VHDL) has its own constructs, each language has its own parsetree. <br /><br />The parsetree is the result of veri_file::Analyze()/vhdl_file::Analyze(). <br /><br />The design parsetree can be "statically elaborated." These are some of the operations during static elaboration process:<br /><br />* Unrolling "generate" loops.<br />* Evaluating constant expressions.<br />* Uniquifying instances of parameterized modules/entities.<br /><br />The result of static elaboration is a modified parsetree.<br /><br />The parsetree supports all constructs of the language.<br /><br /> |
| − | + | ||
# The synthesizable subset of the parsetree can go through "RTL elaboration" (or "synthesis"). The result is the "netlist database," consisting of "hardware" components: libraries, cells, netlists, nets, ports, instances, operators (adders, muxes, ...), and primitives (ands, ors, xors, ...). The netlist database is language-independent. The contents of the netlist database can be written out in various structural languages: Verilog, VHDL, EDIF, BLIF. In general, the output netlist from the netlist database does not look anything like the RTL input files.<br /><br />The netlist database is the result of veri_file::Elaborate()/vhdl_file::Elaborate() API (after veri_file::Analyze()/vhdl_file::Analyze()).<br /><br />RTL elaboration supports the synthesizable subset of the language. | # The synthesizable subset of the parsetree can go through "RTL elaboration" (or "synthesis"). The result is the "netlist database," consisting of "hardware" components: libraries, cells, netlists, nets, ports, instances, operators (adders, muxes, ...), and primitives (ands, ors, xors, ...). The netlist database is language-independent. The contents of the netlist database can be written out in various structural languages: Verilog, VHDL, EDIF, BLIF. In general, the output netlist from the netlist database does not look anything like the RTL input files.<br /><br />The netlist database is the result of veri_file::Elaborate()/vhdl_file::Elaborate() API (after veri_file::Analyze()/vhdl_file::Analyze()).<br /><br />RTL elaboration supports the synthesizable subset of the language. | ||
Revision as of 16:15, 9 May 2019
Q: What are the data structures in Verific?
There are 2 data structures in Verific: parsetree and netlist database.
- The parsetree is just another representation of the design. It contains the exact information as in the RTL files, only in a machine-readable format. Because each language (Verilog or VHDL) has its own constructs, each language has its own parsetree.
The parsetree is the result of veri_file::Analyze()/vhdl_file::Analyze().
The design parsetree can be "statically elaborated." These are some of the operations during static elaboration process:
* Unrolling "generate" loops.
* Evaluating constant expressions.
* Uniquifying instances of parameterized modules/entities.
The result of static elaboration is a modified parsetree.
The parsetree supports all constructs of the language. - The synthesizable subset of the parsetree can go through "RTL elaboration" (or "synthesis"). The result is the "netlist database," consisting of "hardware" components: libraries, cells, netlists, nets, ports, instances, operators (adders, muxes, ...), and primitives (ands, ors, xors, ...). The netlist database is language-independent. The contents of the netlist database can be written out in various structural languages: Verilog, VHDL, EDIF, BLIF. In general, the output netlist from the netlist database does not look anything like the RTL input files.
The netlist database is the result of veri_file::Elaborate()/vhdl_file::Elaborate() API (after veri_file::Analyze()/vhdl_file::Analyze()).
RTL elaboration supports the synthesizable subset of the language.
