Difference between revisions of "How to get packed dimensions of enum"

Revision as of 15:21, 4 July 2019

C++:

#include "Map.h"         // Make associated hash table class Map available
#include "Set.h"         // Make associated hash table class Set available
#include "Message.h"     // Make message handlers available
#include "veri_file.h"   // Make verilog reader available
#include "VeriModule.h"
#include "VeriScope.h"
#include "VeriId.h"
#include "VeriExpression.h"
#include "veri_file.h"
#include <iostream>
#include <string>
#include <string.h>
#include <sstream>
#include <stdio.h>
#include <set>
#include <vector>
#include <map>

using namespace std;
#ifdef VERIFIC_NAMESPACE
using namespace Verific ;
#endif

void GetBaseTypeFromDataType(VeriDataType *);

int main(int argc, char **argv)
{
    veri_file::SetInterfaceModportFieldSeparator("::") ;

    Array file_names;

    if (argc < 2) {
        file_names.InsertLast("test.v");
    } else {
        for (int i = 1; i < argc; i++) {
            file_names.InsertLast(argv[i]);
        }
    }

    Array * file_names_ = new Array( file_names);

    if (!veri_file::AnalyzeMultipleFiles(file_names_, veri_file::SYSTEM_VERILOG, "work", veri_file::MFCU)) {
        std::cout << " Unable to analyze multiple files. Aborting\n";
        return 1 ;
    }

    // Fetching the top module
    Array *top_module_array = veri_file::GetTopModules() ;

    if (!top_module_array) {
        Message::Error(0, "Cannot find any top module in the design") ;
        return 4;
    }

    VeriModule *module = (VeriModule *) top_module_array->GetFirst();

    // Creating VPT
    module->StaticElaborate( 0);
    module->Elaborate( 0, 0, false);

    VeriScope* p_scope = module->GetScope();
    Map* scope_map = p_scope->GetThisScope();
    MapIter mi ;
    VeriIdDef *id;

    FOREACH_MAP_ITEM(scope_map, mi, 0, &id) {
        if (!id ) continue;
        std::cout << "Handling Declaration: "<< id->Name() << std::endl;
        GetBaseTypeFromDataType(id->GetDataType());
    }
    // module->PrettyPrint(std::cout, 1) ;

    return 0;
}


void GetBaseTypeFromDataType(VeriDataType *p_data_type)
{
    if(!p_data_type) {
        return;
    }
    unsigned packed_dim = p_data_type->PackedDimension();
    switch( p_data_type->GetClassId() ) {
        case ID_VERIDATATYPE: {
            std::cout << "===== ID_VERIDATATYPE:: p_data_type->Image() = " << p_data_type->Image() << " =====" << std::endl;
            std::cout << "===== ID_VERIDATATYPE:: packed_dim = " << packed_dim << std::endl;
            if ( packed_dim != 0 ) {
                VeriRange const* range = dynamic_cast<VeriRange const*>
                    (p_data_type->GetDimensions());
                VeriRange const* last_dim_range = NULL;
                do {
                    last_dim_range = range;
                } while ( range && (range = range->GetNext()) );
                    if ( last_dim_range &&  last_dim_range->GetLeft() && last_dim_range->GetRight() ) {
                        std::cout << "packed_dim->Left = " << last_dim_range->GetLeft()->Image() << std::endl;
                        std::cout << "packed_dim->Right = " << last_dim_range->GetRight()->Image() << std::endl;
                    }
                }
                break;
            }
        case ID_VERINETDATATYPE:
        case ID_VERISTRUCTUNION:
        case ID_VERIENUM : {
            std::cout << "===== ID_VERIENUM:: p_data_type->Image() = " << p_data_type->Image() << " =====" << std::endl;
            std::cout << "===== ID_VERIENUM:: packed_dim = " << packed_dim << std::endl;
            if ( packed_dim != 0 ) {
                VeriRange const* range = dynamic_cast<VeriRange const*>
                    (p_data_type->GetDimensions());
                VeriRange const* last_dim_range = NULL;
                do {
                    last_dim_range = range;
                } while ( range && (range = range->GetNext()) );

                if ( last_dim_range &&  last_dim_range->GetLeft() && last_dim_range->GetRight() ) {
                    std::cout << "packed_dim->Left = " << last_dim_range->GetLeft()->Image() << std::endl;
                    std::cout << "packed_dim->Right = " << last_dim_range->GetRight()->Image() << std::endl;
                }
            }
            VeriEnum* p_enum = dynamic_cast<VeriEnum*>(p_data_type);
            VeriDataType* p_base_type = p_enum->GetBaseType();
            GetBaseTypeFromDataType (p_base_type);
            break;
        }
        case ID_VERITYPEREF: {
            std::cout << "===== ID_VERITYPEREF:: p_data_type->Image() = " << p_data_type->Image() << " =====" << std::endl;
            std::cout << "===== ID_VERITYPEREF:: packed_dim = " << packed_dim << std::endl;
            GetBaseTypeFromDataType(p_data_type->GetBaseDataType());
            break;
        }
        default:
            break;
    }
}
 

Input Verilog:

typedef enum bit {a, b} [1:0] data_ctrl_t;

module test (output data_ctrl_t out1 );
    assign out1 = b ;
endmodule
 

Run:

-- Analyzing Verilog file 'test.v' (VERI-1482)
test.v(3): INFO: compiling module 'test' (VERI-1018)
test.v(3): INFO: compiling module 'test' (VERI-1018)
Handling Declaration: out1
===== ID_VERITYPEREF:: p_data_type->Image() = data_ctrl_t =====
===== ID_VERITYPEREF:: packed_dim = 1
===== ID_VERIENUM:: p_data_type->Image() = enum(a,b) =====
===== ID_VERIENUM:: packed_dim = 1
packed_dim->Left = 1
packed_dim->Right = 0
===== ID_VERIDATATYPE:: p_data_type->Image() = bit =====
===== ID_VERIDATATYPE:: packed_dim = 0