Difference between revisions of "Instance - Module binding order"
From Verific Design Automation FAQ
| Line 7: | Line 7: | ||
## -work (present working library) | ## -work (present working library) | ||
## -L | ## -L | ||
| − | ## -y/-v | + | ## -y/-v (their order in an f-file is considered) |
# While elaborating: | # While elaborating: | ||
## configurations | ## configurations | ||
## already resolved module from analysis, ie, order of parsing (above) | ## already resolved module from analysis, ie, order of parsing (above) | ||
Revision as of 10:04, 19 April 2023
Q: Verilog has many ways to find modules not in the file being directly read: -L, -v, -y, .... There may be more than one module of the same name. What is the order of binding?
The order of searching for modules is:
- While parsing:
- `uselib
- -work (present working library)
- -L
- -y/-v (their order in an f-file is considered)
- While elaborating:
- configurations
- already resolved module from analysis, ie, order of parsing (above)
