Constant expression replacement

Q: Does Verific replace constant expressions with their respective values?

I have in my Verilog code:

   parameter size = 8;
   reg [size-1:0] foo;

I expect the range of "foo" to be [7:0]. How do I get the range [7:0]?

If run-time flag "veri_replace_const_exprs" is set, Verific will replace constant expressions with their respective values in static elaboration.

In C++:

RuntimeFlags::SetVar(" veri_replace_const_exprs", 1) ;

In Tcl:

set_runtime_flag "veri_replace_const_exprs" 1