How to use RegisterCallBackMsg()

Here is a small example showing how to use RegisterCallBackMsg():

#include <stdio.h>
#include <stdarg.h>
#include "Strings.h"
#include "Map.h"         // Make associated hash table class Map available
#include "Set.h"         // Make associated hash table class Set available
#include "Message.h"     // Make message handlers available
#include "veri_file.h"   // Make verilog reader available
#include "DataBase.h"    // Make (hierarchical netlist) database API available

#ifdef VERIFIC_NAMESPACE
using namespace Verific ;
#endif

static void MyMsgCallBack (msg_type_t msg_type, const char *message_id, linefile_type linefile, const char *msg, va_list args)
{
     if (msg_type == VERIFIC_WARNING) {
         Message::PrintLine("*** See warning ", message_id) ;
     }
     if (msg_type == VERIFIC_ERROR) {
         Message::PrintLine("*** See error ", message_id) ;
     }
     if (Strings::compare_nocase("VERI-1195", message_id) ) {
         Message::PrintLine("*** See VERI-1195") ;
     }
     if (Strings::compare_nocase("VERI-1207", message_id) ) {
         std::va_list args_tmp0 ;
         va_copy(args_tmp0, args);

         char *modname;
         modname = va_arg(args_tmp0, char *);
         Message::PrintLine("*** See VERI-1207 with unknown module ", modname) ;
         va_end (args_tmp0);
     }
}

int main(int argc, char **argv)
{
    Message::RegisterCallBackMsg(MyMsgCallBack) ;

    veri_file veri_reader ;

    if (argc < 2) Message::PrintLine("reading default input file: test.v. Specify command line argument to override") ;

    const char *file_name = 0 ;
    if (argc>1) {
        file_name = argv[1] ; // Set the file name as specified by the user
    } else {
        file_name = "test.v" ; // Set default file name
    }

    if (!veri_reader.Read(file_name,"work", veri_file::VERILOG_2K)) {
        return 1 ;
    }

    Netlist *top = Netlist::PresentDesign() ;
    if (!top) {
        Message::PrintLine("cannot find any handle to the top-level netlist") ;
        return 1 ;
    }

    Message::Msg(VERIFIC_INFO, 0, top->Linefile(), "top level design is %s(%s)",
                 top->Owner()->Name(), top->Name()) ;

    return 0 ;
}
 

Run:

$ cat test.v
module test (input a, b, output c);
  bot i ();
  botm j ();
  botm m ();
  botm n ();
  assign c = a & b;
  assign c = a ^ b;
endmodule

$ test-linux
-- reading default input file: test.v. Specify command line argument to override
-- Analyzing Verilog file 'test.v' (VERI-1482)
test.v(1): INFO: compiling module 'test' (VERI-1018)
test.v(2): WARNING: instantiating unknown empty module 'bot' (VERI-1207)
-- *** See warning VERI-1207
-- *** See VERI-1207 with unknown module bot
test.v(3): WARNING: instantiating unknown empty module 'botm' (VERI-1207)
-- *** See warning VERI-1207
-- *** See VERI-1207 with unknown module botm
test.v(6): ERROR: net 'c' is constantly driven from multiple places (VDB-1000)
-- *** See error VDB-1000
test.v(7): ERROR: another driver from here (VDB-1001)
-- *** See error VDB-1001
test.v(1): INFO: module 'test' remains a black box, due to errors in its contents (VERI-1073)
test.v(1): INFO: top level design is test()

[hoa@awing0 200514]$