How to parse a string
Let's say you want to add a node to the parsetree.
One of the simple ways to do so is to start with a text string; then "parse" that string to get a VHDL or Verilog construct. The construct then can be added to the parsetree.
Below are the APIs to parse a string:
Verilog:
- VeriExpression *veri_file::AnalyzeExpr(const char *expr, unsigned verilog_mode=VERILOG_2K, const linefile_type line_file = 0)
- VeriModuleItem *veri_file::AnalyzeModuleItem(const char *module_item, unsigned verilog_mode=VERILOG_2K, const linefile_type line_file = 0, VeriScope *container_scope = 0)
- VeriStatement *veri_file::AnalyzeStatement(const char *statement, unsigned verilog_mode=VERILOG_2K, const linefile_type line_file = 0, VeriScope *container_scope = 0)
Appropriate scope information where the given string is valid should be passed to the APIs to have them work properly. Need to call Resolve() on the returned parse tree nodes with proper scope where these items will be used. VeriTreeNode::VERI_UPWARD_SCOPE_NAME can be passed as the resolve environment. If required, they can be added to the existing parse tree using the appropriate APIs.
VHDL:
- VhdlExpression *vhdl_file::AnalyzeExpr(const char *expr, unsigned vhdl_mode=VHDL_93, const linefile_type line_file=0)
- VhdlStatement *vhdl_file::AnalyzeSequentialStatement(const char *statement, unsigned vhdl_mode = VHDL_93, const char *lib_name = "work", const linefile_type line_file = 0, * VhdlScope *container_scope = 0)
- VhdlStatement *vhdl_file::AnalyzeConcurrentStatement(const char *statement, unsigned vhdl_mode = VHDL_93, const char *lib_name = "work", const linefile_type line_file = 0, VhdlScope *container_scope = 0)
- VhdlDesignUnit *vhdl_file::AnalyzeUnit(const char *unit, unsigned vhdl_mode = VHDL_93, const char *lib_name = "work", const linefile_type line_file = 0)
Appropriate scope information where the given string is valid should be passed to the APIs to have them work properly. We need vhdl_file::AnalyzeSequentialStatement() as well as vhdl_file::AnalyzeConcurrentStatement() to differentiate the starting point between the two. Verilog AnalyzeModuleItem() = VHDL AnalyzeConcurrentStatement() and AnalyzeUnit() both Verilog AnalyzeStatement() = VHDL AnalyzeSequentialStatement()
Off-course full designs can be analyzed from strings. Please use streams for that.
See Analyzing Stream Inputs
