Simple example of visitor pattern
From Verific Design Automation FAQ
Revision as of 16:32, 7 December 2020 by Hoa (Talk | contribs) (Created page with " <nowiki> $ cat test.cpp #include <iostream> #include "veri_file.h" #include "VeriModule.h" #include "VeriVisitor.h" #include "VeriConstVal.h" #include "Strings.h" #ifdef V...")
$ cat test.cpp #include <iostream> #include "veri_file.h" #include "VeriModule.h" #include "VeriVisitor.h" #include "VeriConstVal.h" #include "Strings.h" #ifdef VERIFIC_NAMESPACE using namespace Verific ; #endif class MyVisitor : public VeriVisitor { public: MyVisitor() : VeriVisitor() { } virtual ~MyVisitor() { } virtual void VERI_VISIT(VeriConst, node) { char *str = node.GetPrettyPrintedString() ; node.Info("Got expression: %s", str) ; Strings::free(str) ; } } ; int main(int argc, char **argv) { if (!veri_file::Analyze("test.v")) return 1 ; MyVisitor mv ; MapIter mi ; VeriModule *mod ; FOREACH_VERILOG_MODULE(mi, mod) if (mod) mod->Accept(mv) ; return 0 ; } $ cat test.v module test ; (* a = 1, b = 2.6 *) wire w ; assign w = 2'b00 ; endmodule $ test-linux -- Analyzing Verilog file 'test.v' (VERI-1482) test.v(2): INFO: Got expression: 1 test.v(2): INFO: Got expression: 2.6 test.v(3): INFO: Got expression: 2'b0 $