Simple examples of VHDL visitor pattern

$ cat test.cpp
#include "vhdl_file.h"
#include "VhdlUnits.h"
#include "VhdlIdDef.h"
#include "VhdlValue_Elab.h"
#include "Strings.h"

#ifdef VERIFIC_NAMESPACE
using namespace Verific ;
#endif

class MyVisitor : public VhdlVisitor
{
public:
    MyVisitor() : VhdlVisitor() { }
    virtual ~MyVisitor() { }

    virtual void VHDL_VISIT(VhdlConstantId, node)
    {
        VhdlValue *value = node.Value();
        if (value) {
            node.Info("ConstantId: %s, value: %s", node.GetPrettyPrintedString(), value->Image()) ;
        }
    }
} ;

int main ()
{
    vhdl_file::SetDefaultLibraryPath("../vdbs");
    vhdl_file::Analyze("test.vhd", "work");
    vhdl_file::ElaborateAll("work", 1 /* static only */);
    MyVisitor mv ;
    VhdlLibrary *pLib = vhdl_file::GetLibrary("work") ;
    VhdlPrimaryUnit *pPrimaryUnit = pLib->GetPrimUnit("test") ;
    if (pPrimaryUnit) pPrimaryUnit->Accept(mv);
}

$ cat test.vhd
library ieee;
use ieee.std_logic_1164.all;

entity test is
    port (
        d0, d1, d2, d3 : in std_logic_vector (3 downto 0);
        myselect : in std_logic_vector (1 downto 0);
        y : out std_logic_vector (3 downto 0)
    );
end test;

architecture behave of test is
    constant zero : std_logic_vector (1 downto 0) := "00";
    constant one : std_logic_vector (1 downto 0) := "01";
    constant two : std_logic_vector (1 downto 0) := "10";
    constant three : std_logic_vector (1 downto 0) := "11";
begin
    mux: process (myselect, d0, d1, d2, d3)
    begin
        case myselect is
            when zero =>
                y <= d0;
            when one =>
                y <= d1;
            when two =>
                y <= d2;
            when three =>
                y <= d3;
            when others =>
                y <= (others => 'X');
        end case;
    end process mux;
end behave;

$ test-linux
-- Analyzing VHDL file "test.vhd" into library work (VHDL-9003)
INFO: analyzing entity 'test' (VHDL-1012)
test.vhd(6): INFO: Declaration of multiple ports on the same line is valid but can affect code readability (VHDL-9017)
INFO: analyzing architecture 'behave' of entity 'test' (VHDL-9006)
test.vhd(4): INFO: processing 'test(behave)' (VHDL-1067)
test.vhd(13): INFO: ConstantId: zero, value: "00"
test.vhd(14): INFO: ConstantId: one, value: "01"
test.vhd(15): INFO: ConstantId: two, value: "10"
test.vhd(16): INFO: ConstantId: three, value: "11"

$