Yosys-Verific Integration

Yosys is an open source platform that works with a suite of EDA tools. It is possible for a Verific user to integrate Verific with Yosys, which would replace the open source language parsers with Verific's industry-standard ones. Below are several points of interest :

• The minimum requirement to use open source Yosys (as downloaded from YosysHQ https://github.com/yosyshq/yosys) together with Verific software is to have either the VHDL or Verilog/SystemVerilog parser and the RTL elaborator licensed from Verific.

• For users of Verific who have the above minimum configuration and additionally license Verific's Static elaborator, you have the option to purchase a patch of language extensions from YosysHQ to enable basic formal verification functionality in the Yosys open source suite.

• If comprehensive formal verification functionality is desired, the recommended option is to go with the TabbyCAD commercial suite from YosysHQ. A TabbyCAD customer would gain full access to YosysHQ's support, training, and other services.

For more details on integrating with Yosys, please refer to this link :

https://tyrtd.readthedocs.io/en/krys-docs_verific/yosys_internals/extending_yosys/build_verific.html