How to get module ports from Verilog parsetree
From Verific Design Automation FAQ
Revision as of 12:07, 22 July 2016 by Hoa (Talk | contribs) (Created page with "From the Verilog parsetree, how can I get the ports of a module? You can use the following APIs: VeriModule::GetPorts() to get the ports (Array of VeriIdDef *) from a module...")
From the Verilog parsetree, how can I get the ports of a module?
You can use the following APIs:
VeriModule::GetPorts() to get the ports (Array of VeriIdDef *) from a module. VeriIdDef::IsInterfacePort() to check if it is an interface port. VeriDataType::GetEnums(). If it returns non-NULL, the data type is enum. VeriDataType::IsTypeRef() returns 1 for user defined data types.
