How to get all Verilog files being analyzed
From Verific Design Automation FAQ
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Q: I'm using -v, -y, .... After Verific is done with the analysis, how do I get a list of all the files being analyzed?
Use this code:
Array analyzed_files ; // Array to store file-names
unsigned file_id = 1 ; // File-id starts from 1
char *file_name = 0 ;
while ((file_name = LineFile::GetFileNameFromId(file_id++))) {
analyzed_files.InsertLast(file_name) ;
}
// Now analyzed_files array should contain all the files analyzed
How this works:
- Verific keeps file_name vs. file_id mapping.
- File_id starts from 1 and increases by 1.
- LineFile::GetFileNameFromId() returns 0 for non-existing id.
- The code keeps calling the API with increnemted file_id until getting a 0.
You may want to use LineFile::GetAbsFileNameFromId() API instead of LineFile::GetFileNameFromId() if you need absolute filenames (with full path).
