Remove Verific data structures

Q: How do I remove all Verific data structures in memory?

To remove Verilog parsetree:

   veri_file::ResetParser();

To remove VHDL parsetree:

   vhdl_file::ResetParser();

To remove synlib structures:

   synlib_file::Reset();

To remove hierarchy tree:

   hier_tree::DeleteHierarchicalTree() ;

To remove UPF data structures:

   upf_file::DeleteAll();

To remove the netlist database:

   Libset::Reset();

To remove linefile data (make sure that you've removed all parsetrees and the netlist database):

   LineFile::DeleteAllLineFiles();
   LineFile::ResetFileIdMaps();