Instance - Module binding order
From Verific Design Automation FAQ
Revision as of 14:22, 6 April 2017 by Hoa (Talk | contribs) (Created page with "'''Q: Verilog has many ways to find modules not in the file being directly read: -L, -v, -y, .... There may be more than one module of the same name. What is the order of bind...")
Q: Verilog has many ways to find modules not in the file being directly read: -L, -v, -y, .... There may be more than one module of the same name. What is the order of binding?
The order of searching for modules is:
- While parsing:
- `uselib
- -work
- -L
- -y/-v
- While elaborating:
- configurations
- already resolved module from analysis, ie, order of parsing (above)
