Top level module with interface ports
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Q: How to elaborate top-level module with interface ports.
When I elaborate a top-level module with interface ports, Verific issues a warning message and stops the elaboration:
test.sv(10): WARNING: module 'top' having interface port(s) (I) cannot be elaborated by itself (VERI-1554)
How do I elaborate such modules?
Verilog LRM does not allow (elaboration of) top level modules with interface ports. Interface ports need actual interface instance connected to them to elaborate the design.
However, Verific has a runtime flag "veri_elaborate_top_level_modules_having_interface_ports" which when set will elaborate such designs assuming the default interface.
- C++:
RuntimeFlags::SetVar("veri_elaborate_top_level_modules_having_interface_ports", 1) ;
- tcl:
set_runtime_flag "veri_elaborate_top_level_modules_having_interface_ports" 1
