Modules/design units with " default" suffix in their names

Q: After static elaboration, there are modules/design units with "_default" suffix in their names. Why? And what are they?

Static elaboration process is a multiple-iteration process and modules/design units may be modified differently in each iteration.

We need to keep original version of modules/design units as they are immediately after analysis so that they can be copied for different parameter/generic settings in each iteration and body of copied modules/design units can be elaborated (generate unroll, array instance processing, etc.) differently for each parameter/generic setting.

Another reason to copy instantiated modules/design units with "_default" name is in mixed language elaboration. Here a Verilog module may instantiate a VHDL entity which has been elaborated earlier with different generic values. In that case during Verilog elaboration we will not get original contents of instantiated entity.

Moreover, to support incremental elaboration we need to keep original modules/design units, as lower level units can be elaborated earlier.

In Verilog, we have a runtime-flag "veri_remove_suffix_default_from_copied_module_names" to rename modules from "<orig_name>_default" to "<orig_name>". This will work only when runtime-flag "veri_cleanup_base_modules" is set.