How to get all Verilog files being analyzed
From Verific Design Automation FAQ
Q: I'm using -v, -y, .... After Verific is done with the analysis, how do I get a list of all the files being analyzed?
Use this C++:
Array *GetAllAbsFileNames() { Array *files = new Array() ; unsigned file_id = 2 ; // for Verific releases Sep18 and older, use "unsigned file_id = 1 ;" - See VIPER #14058 const char *file_name ; while ((file_name=LineFile::GetAbsFileNameFromId(file_id++))!=0) { // Instead of LineFile::GetAbsFileNameFromId(), the API LineFile::GetFileNameFromId() // can also be used if relative file name is required. // This is a file we processed: files->Insert(file_name) ; } // Now "files" array should contain names of all the files analyzed if (!file->Size()) { delete files ; files = 0 ; } return files ; }
Or this Perl:
my $topfile = "top.v"; # input filename my $stubfile = "stubs.v"; # filename for -v option my $dir = "dir"; # dir name for -y option # Verific::veri_file::AddYDir($dir); # -y option Verific::veri_file::AddVFile($stubfile); # -v option if (!Verific::veri_file::Analyze($topfile)) { exit (1) ; } if (!Verific::veri_file::AnalyzeFull()) { # IMPORTANT: need to call this to process -v, -y, .... exit (1) ; } my $file_id = 2; # for Verific releases Sep18 and older, use "my $file_id = 1;" - See VIPER #14058 # my $file_name=Verific::LineFile::GetAbsFileNameFromId($file_id); # for file with full path $file_name=Verific::LineFile::GetFileNameFromId($file_id); # for just filename while ($file_name ne "") { print "filename analyzed: $file_name\n"; $file_id = $file_id + 1; # $file_name=Verific::LineFile::GetAbsFileNameFromId($file_id); # for file with full path $file_name=Verific::LineFile::GetFileNameFromId($file_id); # for just filename }
How this works:
- Verific keeps file_name vs. file_id mapping.
- File_id starts from 1 and increases by 1.
- LineFile::GetAbsFileNameFromId()/GetFileNameFromId() returns 0 for non-existing id.
- The code keeps calling the API with incremented file_id until getting a 0.