System attributes
From Verific Design Automation FAQ
Verific system attributes are attributes added and attached to DesignObjs (Design Objects) during the process of building the Netlist Database.
To distinguish with user-declared attributes, the key (name) of a system attribute has a space as the first character.
Below is the list of system attributes in the Netlist database. Note that depending on the flow, a DesignObj may or may not have a particular attribute.
Instance (" named_group", named_group) (" GATE_TYPE", "gated_clock") (" creating_port_refs", 0) (" enum_encoding", user_encoding) // DFF (" PROCESS_ID", buffer) // ReadPort/WritePort only (" is_concurrent", "1") // ReadPort/WritePort only (" BLOCKING", "1") // ReadPort/WritePort only Net (" basic_constant", const_val) // is driven by a constant and also connected to a blackbox (" wired", "1") (" is_up_dir", "1") (" original_name", new_name) // for nets renamed due to name confict, original name in the input file (" supply0", 0) // from Verilog "supply0" construct (" supply1", 0) // from Verilog "supply1" construct (" specify_cond", cond_pp) // SDF only (" package_net", "1") (" global_clocking_ref", 0) // SVA (" sva_clock_ref", 0) // SVA (" enum_encoding", user_encoding) NetBus (" original_name", new_name) Port (" orig_port_name", new_name) (" created_from_test_cell", 0) (" open_port", "1") PortBus (" orig_port_name", new_name) Netlist (" language", "edif") // what language it comes from - "edif", "verilog", "vhdl", "upf", "synlib" (" cell_name", module_name) // original module/unit name in input file (" from_netlist_reader", "1") (" primitive", "1") (" unknown_design", "2")) // "1" for Verilog instance, "2" for VHDL instance (" changed_by_interface_overwrite", "1") (" changed_by_hier_ref", "1") (" celldefine","1") (" package", "1") (" upf_uniquified", "1"))
To access the attributes of a DesignObj, use the macro FOREACH_ATTRIBUTE. For example:
DesignObj *design_obj = ....; // or any derived class from DesignObj Att *attr; MapIter mi; FOREACH_ATTRIBUTE(design_obj, mi, attr) { const char *key = (attr) ? attr->Key() : 0 ; if (!key) continue ; if (key[0] == ' ') continue ; // if you want to skip system attributes // Do whatever you want here, e.g. Message::Msg(VERIFIC_INFO, 0, 0, " -- attribute name: %s, value: %s", attr->Key(), attr->Value()); }