How to change name of id in Verilog parsetree

Q:How do I change the name of an id (VeriIdDef) in Verilog parsetree?

Name of identifier can be changed using following steps:

1. Get the scope where identifier is declared (say 'decl_scope').

2. Remove the identifier from its declaration scope:

       decl_scope->Undeclare(id);

3. Change the name of identifier:

       id->SetName("newname");

4. Declare the identifier in decl_scope:

       decl_scope->Declare(id);

Important notes:

Changing the name of an identifier will not always change (the name of) the references. It will only change (appear to have changed) in case the id-ref was resolved before the name change.

In the analyzed parse tree, an id ref will not be resolved in the following cases (there may be some more):

- Reference is in instantiated module name (instantiated module may change via configuration).

- Reference to something declared within for-generate (have multiple existence of the identifier).

- Reference via hier-ref and not a direct ref (only resolved during static elaboration). Even a static elaborated tree will not have the effect since we do not free _suffix and do not print _suffix_id from pretty print.

- Reference via actual of a bind instance (resolving needs to be done in the bounded context and not in the declaration context).

Only simple, local and direct references are resolved.

Also, since Verific does not have a ref to def back pointers (which the analyze parsetree can't have anyway), there is no good way to change the name of the id along with all of its references.

This can only be done in static elaborated tree but have to visit all VeriSelectedName to change the _suffix as well. This is a bit complicated.