Notes on analysis

This is a place holder for notes regarding analysis of System Verilog designs.

Can I use veri_file::Analyze to read SV input files one by one?

Yes. But if you have multiple files, it’s better to use veri_file::AnalyzeMultipleFiles().

veri_file::AnalyzeMultipleFiles(), besides analyzing each files, also:

- opens and ends the compilation unit
- processes –v and –y options
- removes include directories
- processes root module
- undefines user-defined macros
- resets compile directives (e.g. `default_nettype, `timescale)

If you use veri_file::Analyze() to analyze files one by one. After parsing all the files and before elaboration, you’ll need to call:

- veri_file::ProcessUserLibraries()
- veri_file::RemoveAllIncludeDirs()
- veri_file::EndCompilationUnit ()