Notes on analysis

This is a place holder for notes regarding analysis of System Verilog designs.

First, please read

Can I use veri_file::Analyze to read System Verilog input files one by one?

Yes. But if you have multiple files, it’s better to use veri_file::AnalyzeMultipleFiles().

veri_file::AnalyzeMultipleFiles(), besides analyzing each files, also:

• opens and ends the compilation unit
• processes –v and –y options
• removes include directories
• processes root module
• undefines user-defined macros
• resets compile directives (e.g. `default_nettype, `timescale)

If you use veri_file::Analyze() to analyze files one by one, after parsing all the files and before elaboration, you’ll need to call these APIs:

• veri_file::ProcessUserLibraries()
• veri_file::RemoveAllIncludeDirs()
• veri_file::EndCompilationUnit ()