Parse select modules only and ignore the rest

There is no API to parse only a subset of modules of a design that contains many modules. However, this can be accomplished through Verific's processing of v-files.

Below is an outline of the steps involved:

- Register all the input source files as v-files for processing.
- Move all of the modules to the 'work' library.
- Analyze a 'dummy' file that contains only the modules of interest.
- Process the v-files

C++:

#include <iostream>
#include "veri_file.h"
#include "VeriModule.h"
#include "VeriLibrary.h"
#include "Map.h"

#ifdef VERIFIC_NAMESPACE
using namespace Verific ;
#endif

int main()
{
    // Add the 'real' input file(s) to be analyzed as -v file:
    veri_file::AddVFile("testa.v") ;
    veri_file::AddVFile("testb.v") ;
    // Move -v modules into 'work'
    RuntimeFlags::SetVar("veri_move_yv_modules_into_work_library", 1) ;

    // Analyze dummy file
    if (!veri_file::Analyze("dummy.v", veri_file::SYSTEM_VERILOG)) return 1 ;
    // Need this to process -v file
    veri_file::ProcessUserLibraries() ;

    VeriModule *dummy = veri_file::GetModule ("dummy") ;
    delete dummy ; // no longer needed

    MapIter mi;
    VeriModule *module;
    FOREACH_VERILOG_MODULE (mi, module) {
        std::cout << "*** Module '" << module->Name() << "' in library '" << module->GetLibrary()->GetName() << "'" << s
td::endl ;
    }
    veri_file::PrettyPrint("pp_out.v", 0) ;
    return 0 ;
}
 

Source file testa.v:

module test1 ;
    wire ina, inb, inc;
    wire outd;
    mod1 I0(ina, inb, inc, outd);
endmodule

module test2 ;
    wire ina, inb, inc;
    wire outd;
    mod2 I0(ina, inb, inc, outd);
endmodule
 

Source file testb.v:

module test3 ;
    wire ina, inb, inc;
    wire outd;
    mod3 I0(ina, inb, inc, outd);
endmodule

module test4 ;
    wire ina, inb, inc;
    wire outd;
    mod4 I0(ina, inb, inc, outd);
endmodule

module test5 ;
    wire ina, inb, inc;
    wire outd;
    mod5 I0(ina, inb, inc, outd);
endmodule
 

Result of running the application:

-- Analyzing Verilog file 'dummy.v' (VERI-1482)
-- Analyzing Verilog file 'testa.v' (VERI-1482)
--       Resolving module 'test2' (VERI-1489)
-- Analyzing Verilog file 'testb.v' (VERI-1482)
--       Resolving module 'test3' (VERI-1489)
-- Analyzing Verilog file 'testa.v' (VERI-1482)
-- Analyzing Verilog file 'testb.v' (VERI-1482)
*** Module 'test2' in library 'work'
*** Module 'test3' in library 'work'
-- Printing all libraries to file 'pp_out.v' (VERI-1492)
 

Output file pp_out.v:

module test2 ;
    wire ina, inb, inc ; 
    wire outd ; 
    mod2 I0 (ina, inb, inc, outd) ; 
endmodule



module test3 ;
    wire ina, inb, inc ; 
    wire outd ; 
    mod3 I0 (ina, inb, inc, outd) ; 
endmodule