Instance - Module binding order

Q: Verilog has many ways to find modules not in the file being directly read: -L, -v, -y, .... There may be more than one module of the same name. What is the order of binding?

The order of searching for modules is:

1. While parsing:
   1. `uselib
   2. -L
   3. -work
   4. -y/-v
2. While elaborating:
   1. configurations
   2. already resolved module from analysis, ie, order of parsing (above)