Modules/design units with " default" suffix in their names
Q: After static elaboration, there are modules/design units with "_default" suffix in their names. Why? And what are they?
Static elaboration process is a multiple-iteration process and modules/design units may be modified differently in each iteration.
We need to keep original version of modules/design units as they are immediately after analysis so that they can be copied for different parameter/generic settings in each iteration and body of copied modules/design units can be elaborated (generate unroll, array instance processing, etc.) differently for each parameter/generic setting.
Another reason to copy instantiated modules/design units with "_default" name is in mixed language elaboration. Here a Verilog module may instantiate a VHDL entity which has been elaborated earlier with different generic values. In that case during Verilog elaboration we will not get original contents of instantiated entity.
Moreover, to support incremental elaboration we need to keep original modules/design units, as lower level units can be elaborated earlier.
In Verilog, we have a runtime-flag "veri_remove_suffix_default_from_copied_module_names" to rename modules from "<orig_name>_default" to "<orig_name>". This will work only when runtime-flag "veri_cleanup_base_modules" is set.
Q: What about interfaces with "_default" suffix in their names? Why? And what are they?
SystemVerilog interfaces can be used in any of the following ways :
- As interface instantiations.
- As interface ports.
- As virtual interfaces.
- As hierarchical names.
If an interface is used in a virtual interface declaration, interface instance, or port of a top-level module, the interface will be copied to '<interface_name>_default', even if none of its parameters are overwritten. This copied interface will be the one that is elaborated and specified in the virtual interface declaration, interface instance, or top-level module port. Every instantiated module containing interface type ports will also be copied during static elaboration since its interface port names may have been modified as well.
Virtual interfaces can appear in many different parts of a design, and may or may not be associated with interface instances. Virtual interfaces are not stored in Verific's pseudo-tree, so after static elaboration we do not know whether an interface is used as a virtual interface or not, or where it is being used. Without this knowledge, we cannot arbitrarily change all the references of an interface from '<interface_name>_default' to '<interface_name> because the references may become invalid. Because of this, we do not have flags to remove the '_default' from the interface names as we do for modules.
The '_default_<n>' suffix may also be added due to the presence of hierarchical references in an interface or bind statements containing interface instantiations.
