Simple port modification
From Verific Design Automation FAQ
Revision as of 15:59, 11 October 2024 by Mohammad (Talk | contribs) (Created page with "This example converts module with struct ports into flat ports. <nowiki> from invio import * set_preference("invio_insert_ports_with_newline", 1) add_sv_file("test.sv") ana...")
This example converts module with struct ports into flat ports.
from invio import * set_preference("invio_insert_ports_with_newline", 1) add_sv_file("test.sv") analyze() elaborate("top") # Convert top module with struct ports into flat ports top_module_obj = get_modules("top").first for p in get_ports(top_module_obj): #report_attributes(p) # for debugging purposes you can print the attributes and see what is going on p_type = p.data_type # Filter the user type ports if (p_type.is_named_user_type): # Create new ports for each memeber and add them to the module for m in p_type.members: dims = [] for d in m.dimensions: dims.append( (d.left_index, d.right_index) ) # Create a port with the same attributes as struct memebers new_port = create_port(m.base_name, p.direction, datatype_name=m.data_type_name, dimensions=dims); # Insert them into top module insert_into(new_port, top_module_obj) # Delete the old struct port delete_object(p) # Write out the modifications write_modified_file("test.sv", "test_mod.sv")
"test.sv"
typedef struct { logic clk; logic rst; logic [1:0] addr; int data; } bus_t; // Convert the struct port into flat ports module top #(WIDTH = 4)( input bus_t in_bus, // this one output [0:WIDTH-1] d, input [0:WIDTH-1] a ) ; endmodule
Testcase after modification, "test_mod.sv":
typedef struct { logic clk; logic rst; logic [1:0] addr; int data; } bus_t; // Convert the struct port into flat ports module top #(WIDTH = 4)( output [0:WIDTH-1] d, input [0:WIDTH-1] a, input logic clk, input logic rst, input logic [1:0] addr, input int data ) ; endmodule