How to get enums from Verilog parsetree
From Verific Design Automation FAQ
Q: From the parsetree, how can I get the enums declared in a module?
You can use the following code snippet:
VeriModule *mod = ... ; VeriScope *scope = mod->GetScope() ; Set ids(POINTER_HASH) ; if (scope) scope->GetDeclaredIds(ids) ; SetIter si ; VeriIdDef *id ; FOREACH_SET_ITEM(&ids, si, &id) { if (!id->IsEnumId()) continue ; // Here id is an enum id/literal. // id->GetInitialValue() returns the use specified initial value of the enum id // If there is no value specified in the input RTL, you get a NULL returned. }