Preserving user nets - preventing nets from being optimized away

Q: How do I preserve user-declared nets so that they don't get optimized away? I would like to see them written out to the netlist file.

There are two approaches :

• globally preserve all user nets
• preserve only selective nets

1. Globally preserve all user nets

The following flags need to be set to have global effect :

set_runtime_flag db_preserve_user_nets 1
set_runtime_flag veri_preserve_user_nets 1      # if using Verilog/SystemVerilog
set_runtime_flag vhdl_preserve_user_nets 1      # if using VHDL

2. Preserve only selective nets

Setting an attribute on a net will prevent it from being optimized away. The attribute can be any attribute, as seen in the examples below.

Verilog :

module test (input i, output o);
  (* any *) wire willstay;
  wire willgo;
  (* another = "any" *) reg willstaytoo;
  assign o = ~i;
endmodule

This is the output Verilog netlist :

//
// Verific Verilog Description of module test
//
module test (i, o);   // test2.v(1)
   input i;   // test2.v(1)
   output o;   // test2.v(1)
   
   wire willstay /* verific any=1 */ ;   // test2.v(2)
   wire willstaytoo /* verific another="any" */ ;   // test2.v(4)
   
   not (o, i) ;   // test2.v(5)
   
endmodule

VHDL :

library ieee;
use ieee.std_logic_1164.all ;
entity test is 
   port (i : in bit; o : out bit) ;
end entity test;
architecture arch of test is
   signal willstay : bit ;
   signal willgo : bit ;
   signal willstaytoo : bit ; 
   attribute any : string ;
   attribute any of willstay : signal is "" ;
   attribute another : string ;
   attribute another of willstaytoo : signal is "any" ;
begin
   o <= not i ;
end arch ;

This is the output VHDL netlist :

--
-- Verific VHDL Description of module test
--
library ieee ;
use ieee.std_logic_1164.all ;
entity test is
    port (i: in std_logic;   -- test2.vhd(4)
        o: out std_logic   -- test2.vhd(4)
    );
end entity test;   -- test2.vhd(3)
architecture arch of test is 
    signal willstay : std_logic; -- any=""    -- test2.vhd(8)
    signal willstaytoo : std_logic; -- another="any"    -- test2.vhd(10) 
begin
    o <= not i;   -- test2.vhd(16)  
end architecture arch;   -- test2.vhd(3)