VHDL, Verilog, Liberty, EDIF

Q: I'm using -v, -y, .... After Verific is done with the analysis, how do I get a list of all the files being analyzed?

Use this code:

Array analyzed_files ; // Array to store file-names
unsigned file_id = 1 ; // File-id starts from 1
char *file_name = 0 ;
while ((file_name = LineFile::GetFileNameFromId(file_id++))) {
         analyzed_files.InsertLast(file_name) ;
}
// Now analyzed_files array should contain all the files analyzed

How this works:

1. Verific keeps file_name vs. file_id mapping.
2. File_id starts from 1 and increases by 1.
3. LineFile::GetFileNameFromId() returns 0 for non-existing id.
4. The code keeps calling the API with increnemted file_id until getting a 0.

You may want to use LineFile::GetAbsFileNameFromId() API instead of LineFile::GetFileNameFromId() if you need absolute filenames (with full path).

Q: While looking at a Netlist, is there a clean way to look back at what VeriModule* or VhdlPrimaryUnit* this netlist was derived from?

For example, a module:

   module mod();
   parameter WIDTH=2;
   ...
   endmodule

would elaborate to a netlist name \mod(WIDTH=2) or if instantiated with a different width \mod(WIDTH=4)

There are "system" attributes attached to the Netlist that you may find useful. Note the leading space:

key: " language", value: one of "verilog" "vhdl".

key: " cell_name", value: original module/unit name.

See also Netlist::CellBaseName().

Once you get the original name of the module/unit, you can search the parse tree for it.

Q: Why are the ports in original Verilog file renamed to p1, p2, ....?

Input file:

   module foo ( datain[0],  datain[0] /* same net into multiple port expression */,
                datain[2:1]  /* part-select  port expression */,
                /* empty port expression */,
                {datain[2],datain[1], datain[1]} /* concatenation in port expression */
               ) ;
       input [2:0] datain ;
       ...
   endmodule

Output netlist:

   module foo (p1, p2, p3, , p7);   // test.v(1[8:11])
       input p1;   // test.v(6[17:23])
       input p2;   // test.v(6[17:23])
       input [1:0]p3;
       input [2:0]p7;
       ...     
   endmodule

The items in the () after the module name are not "port names," rather, they are "port expressions." Verilog defines that the port expressions on this module CANNOT be accessed by name (only by order). This means you cannot rely on the port names to be one thing or another.

Verific chose to not adjust to any particular naming scheme for complex port expressions, which also allows us to error out if named port instantiation occurs where the language disallows it.

The original port expression of the renamed port is saved as attributes " orig_port_name" attached to the port.

   key: " orig_port_name", value: port expression

For the testcase above:

   input p1 /* verific  orig_port_name=datain[0] */ ;
   input p2 /* verific  orig_port_name=datain[0] */ ;
   input [1:0]p3 /* verific  orig_port_name=datain[2] datain[1] */ ;
   input [2:0]p7 /* verific  orig_port_name=datain[2] datain[1] datain[1] */ ;

Q: I have a design consisting of a mixture of Verilog 2001 and SystemVerilog input files. Should I parse all the files as SystemVerilog?

The set of SystemVerilog constructs is a superset of the set of Verilog 2001 constructs. As a corollary, the set of SystemVerilog keywords is a superset of the set of Verilog 2001 keywords.

Parsing a Verilog 2001 file as SystemVerilog will work, as long as the file does not use any SystemVerilog keyword as identifier. If you parse the file as SystemVerilog an run into a syntax error, try parsing it as Verilog 2001.

Another significant difference between Verilog 2001 and SystemVerilog is "compilation units." The default mode of Verilog 2001 is "multi-file" while the default mode of SystemVerilog is "single-file." For more details, please read:

http://www.verific.com/docs/index.php?title=Single/Multi-File_Compilation_Units

Q: A customer wants to analyze/elaborate different VHDL flavors (1993 and 2008). They want to process the 93 files first and then the 08. As each flavor has its own IEEE library set, do you have any suggestion on how to handle this scenario?

A: Please load the 2008 version of the IEEE library distributed by Verific and then analyze the 1993 and 2008 design files in their proper dialect. Verific will internally adjust the packages and both the designs should compile without any errors. For example:

   setvhdllibrarypath -default verific_source/vhdl_packages/vdbs_2008
   analyze test93.vhdl
   analyze -vhdl_2008 test2008.vhdl

For more details, see http://www.verific.com/w/index.php/VHDL-1993_versus_VHDL-2008_IEEE_packages